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1 of 76 rev: 090104 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds21q59 e1 quad transceiver contains all the necessary functions for connecting to four e1 lines. the ds21q59 is a direct replacement for the ds21q50, with the addition of signaling access and improved interrupt handling. it is composed of a line interface unit (liu), framer, and a tdm backplane interface, and is controlled through an 8-bit parallel port configured for intel or motorola bus operations or serial port operation. applications dslams routers ima and wan equipment pin configuration features four complete e1 (c ept) pcm-30/isdn-pri transceivers pin compatible with the ds21q50 long-haul and short-haul line interfaces 32-bit or 128-bit crystal-less jitter attenuator frames to fas, cas, and crc4 formats cas/ccs signaling support 4mhz/8mhz/16mhz clock synthesizer flexible system clock with automatic source switching on loss-of-clock source two-frame elastic-store slip buffer on the receive side interleaving pcm bus operation up to 16.384mhz configurable parallel and serial port operation detects and generates remote and ais alarms fully independent transmit and receive functionality four separate loopback functions prbs generation/detection/error counting 3.3v low-power cmos large counters for bipolar and code violations, crc4 codeword errors, fas word errors, and e bits eight additional user-configurable output pins 100-pin (14mm) lqfp package ordering information part temp range pin-package ds21q59l 0c to +70c 100 lqfp DS21Q59LN -40c to +85c 100 lqfp lqfp 1 100 dallas semiconducto r ds21q59 top view ds21q59 e1 quad transceive r www.maxim-ic.com
ds21q59 quad e1 transceiver 2 of 76 table of contents 1. acronyms ....................................................................................................................... 6 2. detailed description.................................................................................................6 3. block diag ram .............................................................................................................7 4. pin descri ption.............................................................................................................8 4.1 p in f unction d escriptions ......................................................................................................12 5. functional description .........................................................................................13 6. host interface port................................................................................................14 6.1 p arallel p ort o peration .......................................................................................................14 6.2 s erial p ort o peration ............................................................................................................14 7. register map...............................................................................................................16 8. control, id, and t est registers .........................................................................17 8.1 p ower -u p s equence ................................................................................................................18 8.2 f ramer l oopback ....................................................................................................................21 8.3 a utomatic a larm g eneration .................................................................................................22 8.4 r emote l oopback ....................................................................................................................22 8.5 l ocal l oopback .......................................................................................................................23 9. status and inform ation registers ...................................................................27 9.1 i nterrupt h andling .................................................................................................................28 9.2 crc4 s ync c ounter ................................................................................................................29 10. error count registers..........................................................................................34 10.1 bpv or cv c ounter .............................................................................................................34 10.2 crc4 e rror c ounter ..........................................................................................................34 10.3 e-b it /prbs b it -e rror c ounter ..........................................................................................35 10.4 fas e rror c ounter .............................................................................................................35 11. signaling operation................................................................................................36 11.1 r eceive s ignaling .................................................................................................................36 11.2 t ransmit s ignaling ...............................................................................................................36 11.3 cas o peration .....................................................................................................................36 12. ds0 monitoring function .......................................................................................37 13. prbs generation and detection.........................................................................39 14. system clock interface ........................................................................................40 15. transmit cl ock source..........................................................................................41 16. idle code insertion ..................................................................................................41
ds21q59 quad e1 transceiver 3 of 76 17. per-channel loopback ..........................................................................................42 18. elastic store operation .......................................................................................42 19. additional (sa) and international (si) bit operation..................................43 20. user-configurabl e outputs ................................................................................45 21. line interface unit ...................................................................................................47 21.1 r eceive c lock and d ata r ecovery .....................................................................................47 21.1.1 termination .................................................................................................................... .......................47 21.2 t ransmit w aveshaping and l ine d riving .............................................................................48 21.3 j itter a ttenuators ..............................................................................................................50 21.3.1 clock and data jitter attenuators .............................................................................................. ...........50 21.3.2 undedicated clock jitter attenuator ............................................................................................ .........51 22. code mark inversion (cmi) .....................................................................................52 23. interleaved pcm bus operation .........................................................................54 24. functional timing diagrams.................................................................................56 24.1 r eceive ............................................................................................................................... ...56 24.2 t ransmit ............................................................................................................................... .58 25. operating parameters...........................................................................................62 26. ac timing paramete rs and diagrams ................................................................63 26.1 m ultiplexed b us ac c haracteristics .................................................................................63 26.2 n onmultiplexed b us ac c haracteristics ..........................................................................66 26.3 s erial p ort ...........................................................................................................................68 26.4 r eceive ac c haracteristics ...............................................................................................69 26.5 t ransmit ac c haracteristics .............................................................................................72 26.6 s pecial m odes ac c haracteristics ....................................................................................74 27. package information..............................................................................................75 28. revision hi story ........................................................................................................76
ds21q59 quad e1 transceiver 4 of 76 list of figures figure 3-1. block diagram ...................................................................................................... ................. 7 figure 6-1. serial po rt operati on mode 1 ....................................................................................... ........14 figure 6-2. serial po rt operati on mode 2 ....................................................................................... ........15 figure 6-3. serial po rt operati on mode 3 ....................................................................................... ........15 figure 6-4. serial po rt operati on mode 4 ....................................................................................... ........15 figure 21-1. external analog c onnections (basic c onfigurat ion) ...........................................................48 figure 21-2. external analog c onnections (protect ed interf ace) ............................................................49 figure 21-3. transmit waveform template ........................................................................................ ....50 figure 21-4. jitter tolerance.................................................................................................. .................51 figure 21-5. jitter attenuation ................................................................................................ ................51 figure 22-1. cmi coding ........................................................................................................ ................52 figure 22-2. example of cmi code viol ation (cv)................................................................................ ..53 figure 23-1. ibo configuration using two ds21q59 transceivers (eight e1 lines)..............................55 figure 24-1. receive frame and multiframe timing ............................................................................... 56 figure 24-2. receive boundary timing (with elastic store dis abled) .....................................................56 figure 24-3. receive boundary timing (with elastic store e nabled) .....................................................56 figure 24-4. receive interleave bus operation .................................................................................. ....57 figure 24-5. transmit frame and multiframe timing .............................................................................. 58 figure 24-6. trans mit boundary timing.......................................................................................... ........58 figure 24-7. transmit interleave bus operation ................................................................................. ....59 figure 24-8. framer synchronization flowchart .................................................................................. ...60 figure 24-9. transmit data flow ................................................................................................ ............61 figure 26-1. intel bus read ac timing (pbts = 0)............................................................................... .64 figure 26-2. intel bus write timing (pbts = 0)................................................................................. .....64 figure 26-3. motorola bus ac timing (pbts = 1) ................................................................................. .65 figure 26-4. intel bus read timing (pbts = 0).................................................................................. ....66 figure 26-5. intel bus write timing (pbts = 0)................................................................................. .....67 figure 26-6. motorola bu s read timing (pbts = 1)............................................................................... 67 figure 26-7. motorola bus write timing (pbts = 1).............................................................................. .67 figure 26-8. serial bus timing (bts1 = 1, bts0 = 0) ............................................................................ 68 figure 26-9. receive ac timing (receive elastic store disabled) .........................................................70 figure 26-10. receive ac timing (r eceive elastic store e nabled) ........................................................71 figure 22-11. transmit ac timing (ibo disabled)................................................................................ ..73 figure 22-12. transmit ac timing (ibo enabl ed) ................................................................................. .74 figure 26-13. nrz input ac timing .............................................................................................. .........74
ds21q59 quad e1 transceiver 5 of 76 list of tables table 4-a. pin description (sorted by function) ................................................................................ ...... 8 table 4-b. pin assignments (sorted by number) .................................................................................. .10 table 4-c. system (bac kplane) inte rface pins ................................................................................... ....12 table 4-d. alternate jitter at tenuato r ......................................................................................... ............12 table 4-e. clock synthesizer ................................................................................................... ..............12 table 4-f. parallel port control pins .......................................................................................... ............12 table 4-g. serial port control pins............................................................................................ .............13 table 4-h. line interface pins ................................................................................................. ...............13 table 4-i. supply pins ......................................................................................................... ...................13 table 6-a. bu s mode se lect ..................................................................................................... ..............14 table 7-a. register map (sorted by address) .................................................................................... ....16 table 8-a. sync/resync criteria................................................................................................ .............19 table 8-b. g. 703 func tion...................................................................................................... ................24 table 8-c. ou tput modes ........................................................................................................ ...............25 table 9-a. alarm criteria ...................................................................................................... ..................29 table 13-a. transmit prbs mode select.......................................................................................... .....39 table 13-b. receiv e prbs mode select........................................................................................... .....39 table 14-a. synthesizer output select.......................................................................................... .........40 table 14-b. system clock selection............................................................................................. ..........40 table 20-a. outa and ou tb functi on sele ct ...................................................................................... .46 table 21-a. line build-out select in licr...................................................................................... ........48 table 21-b. transformer specifications......................................................................................... .........48 table 23-a. ibo system clock select ............................................................................................ ........54 table 23-b. ibo device assignment .............................................................................................. ........54 table 26-a. ac characteristi cs?multiplexed pa rallel port .....................................................................63 table 26-b. ac characteristics?n onmultiplexed pa rallel port ..............................................................66 table 26-c. ac characteristics?seria l port (bts1 = 1, bts0 = 0) .......................................................68 table 26-d. ac charac teristics?r eceive r........................................................................................ .....69 table 26-e. ac characteristics?transmit ........................................................................................ .....72 table 26-f. ac charac teristics?spec ial m odes ................................................................................... .74
ds21q59 quad e1 transceiver 6 of 76 1. acronyms the following abbreviations are used throughout this data sheet: fas frame alignment signal cas channel associated signaling mf multiframe si international bits crc4 cyclical redundancy check ccs common channel signaling sa additional bits e-bit crc4 error bits loc loss of clock tclk this generally refers to the transmit rate clock and can reference an actual input signal to the device (tclk) or an internally derived signal used for transmission. rclk this generally refers to the recovered network clock and can be a reference to an actual output signal from the device or an internal signal. 2. detailed description the liu is composed of a transmit interface, receive interface, and a jitter attenuator. the transmit interface generates the necessary waveshapes for driving the network, depending on the type of media used. e1 waveform generation includes g.703 waveshapes for both 75 coax and 120 twisted cables. the receive interface recovers clock and data from the network. the receive sensitivity adjusts automatically to the incoming signal. the jitter attenuator removes phase jitter from the transmitted or received signal. the crystal-less jitter attenuator only requires a 2.048mhz mclk and can be placed in either the transmit or receive data paths. an additional feature of the liu is a code mark inversion (cmi) coder/decoder for interfacing to optical networks. on the transmit side, the backplane interface section provides clock/data and frame-sync signals to the framer. the framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the crc codes, and provides the hdb3 (zero code suppression) and alternate mark inversion (ami) line coding. the receive-side framer decodes ami and hdb3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/crc errors, and provi des clock/data and frame-sync signals to the backplane interface section. the backplane interface provides a versatile method of sending and receiving data from the host system. the receive elastic store provides a method for interfacing to asynchronous systems. the elastic store also manages slip conditions (asynchronous interface). an interleave bus option (ibo) is provided to allow multiple e1 lines to share a high-speed backplane. the parallel port provides access for control and configuration of all the ds21q59?s features. diagnostic capabilities include loopbacks, prbs pattern generation /detection, and 16-bit l oop-up and loop-down code generation and detection. the device fully meets all the latest e1 specifications, including itu-t g.703, g.704, g.706, g.823, g.732 and i.431 ets 300 011, ets 300 233, and ets 300 166 as well as ctr12 and ctr4. the ds21q59 is optimized for high-density termination of e1 lines. two significant features are included for this type of application: the ibo and a system clock synthesizer feature. the ibo allows up to eight e1 data streams to be multiplexed onto a single high-speed pcm bus without additional external logic. the system clock synthesizer allows any of the e1 lines to be selected as the master source of the clock for the system and for all the transmitters. this is also accomplished without the need of external logic. each of the four transceivers has a clock and data jitter attenuator that can be assigned to either the transmit or receive path. in addition there is a single, undedicated clock jitter attenuator that can be hardware configured as needed by the user. each transceiver also contains a prbs pattern generator and detector. figure 23-1 shows a simplified typical application that terminates eight e1 lines (transmit and receive pairs) and combines the data into a single 16.384mhz pcm bus. the 16.384mhz system clock is derived and phase-locked to one of the eight e1 lines. on the receive side of each port, an elastic store provides logical management of any slip conditions due to the asynchronous relationship of the eight e1 lines. in this application all eight transmitters are timed to the selected e1 line.
ds21q59 quad e1 transceiver 7 of 76 3. block diagram figure 3-1. block diagram ale(as)/a5 rring1 receive-side framer transmit- side formatter tclk1 tser1 rser1 sysclk1 rsync1 elastic store and ibo buffer tring1 ttip1 jitter attenuator either transmit or receive path receive line i/f clock/data recovery rtip1 vco/pll line i/f transmit data clock sync sync clock data ibo buffer divide- by-2/4/8 mclk tsync1 sync control bu ck mux tx ck mux a b a b c user output select outa1 outb1 rclk transceiver 2 rclk transceiver 3 rclk transceiver 4 mux 4/8/16mhz synthesizer backup clock mux transceivers 2, 3, 4 4/8/16mck refclk system clock interface transmit clock source transceiver 1 of 4 transmit side receive side local loopback remote loopback framer loopbac k lotc detect 2.048mhz d0?d7 / ad0?ad7 ts1 in t wr (r/ w ) rd ( ds ) c s a0?a4 parallel and test control port ( routed to all blocks ) bts1 bts0 ts0 pbts ajacoi ajacki alternate jitter attenuator dallas semiconductor ds21q59
ds21q59 quad e1 transceiver 8 of 76 4. pin description table 4-a. pin description (sorted by function) name pin parallel port enabled serial port enabled type function [serial port mode in brackets] 71 4/8/16mck ? o 4.096mhz, 8.192mhz, or 16.384mhz clock 45 a0 ices i address bus bit 0/serial port [input-clock edge select] 46 a1 oces i address bus bit 1/serial port [output-clock edge select] 47 a2 ? i address bus bit 2 48 a3 ? i address bus bit 3 49 a4 ? i address bus bit 4 70 ajacki ? i alternate jitter attenuator clock input 69 ajacko ? o alternate jitter attenuator clock output 50 ale (as)/a5 ? i address latch enable/address bus bit 5 96 bts0 ? bus type select 0 97 bts1 ? bus type select 1 98 cs ? i chip select 19 d0/ad0 ? i/o data bus bit 0/address/data bus bit 0 20 d1/ad1 ? i/o data bus bit 1/address/data bus bit 1 21 d2/ad2 ? i/o data bus bit 2/address/data bus bit 2 22 d3/ad3 ? i/o data bus bit 3/address/data bus bit 3 23 d4/ad4 ? i/o data bus bit 4/address/data bus bit 4 24 d5/ad5 ? i/o data bus bit 5/address/data bus bit 5 25 d6/ad6 ? i/o data bus bit 6/address/data bus bit 6 44 d7/ad7 sdo i/o data bus bit 7/addres s/data bus bit 7 [serial data output] 84 dvdd1 ? ? digital positive supply 59 dvdd2 ? ? digital positive supply 34 dvdd3 ? ? digital positive supply 9 dvdd4 ? ? digital positive supply 83 dvss1 ? ? digital signal ground 58 dvss2 ? ? digital signal ground 33 dvss3 ? ? digital signal ground 8 dvss4 ? ? digital signal ground 94 int ? o interrupt 73 mclk ? i master clock input 61 outa1 ? o user-selectable output a 36 outa2 ? o user-selectable output a 11 outa3 ? o user-selectable output a 86 outa4 ? o user-selectable output a 60 outb1 ? o user-selectable output b 35 outb2 ? o user-selectable output b 10 outb3 ? o user-selectable output b 85 outb4 ? o user-selectable output b 95 pbts ? i parallel bus type select 75 rd ( ds ) sclk i read input (data strobe) [serial port clock] 72 refclk ? i/o reference clock 67 rring1 ? i receive analog ring input 42 rring2 ? i receive analog ring input 17 rring3 ? i receive analog ring input 92 rring4 ? i receive analog ring input 63 rser1 ? o receive serial data 38 rser2 ? o receive serial data 13 rser3 ? o receive serial data 88 rser4 ? o receive serial data 64 rsync1 ? i/o receive sync 39 rsync2 ? i/o receive sync 14 rsync3 ? i/o receive sync
ds21q59 quad e1 transceiver 9 of 76 name pin parallel port enabled serial port enabled type function [serial port mode in brackets] 89 rsync4 ? i/o receive sync 66 rtip1 ? i receive analog tip input 41 rtip2 ? i receive analog tip input 16 rtip3 ? i receive analog tip input 91 rtip4 ? i receive analog tip input 93 rvdd1 ? ? receive analog positive supply 68 rvdd2 ? ? receive analog positive supply 43 rvdd3 ? ? receive analog positive supply 18 rvdd4 ? ? receive analog positive supply 90 rvss1 ? ? receive analog signal ground 65 rvss2 ? ? receive analog signal ground 40 rvss3 ? ? receive analog signal ground 15 rvss4 ? ? receive analog signal ground 62 sysclk1 ? i transmit/receive system clock 37 sysclk2 ? i transmit/receive system clock 12 sysclk3 ? i transmit/receive system clock 87 sysclk4 ? i transmit/receive system clock 80 tclk1 ? i transmit clock 55 tclk2 ? i transmit clock 30 tclk3 ? i transmit clock 5 tclk4 ? i transmit clock 79 tring1 ? o transmit analog ring output 54 tring2 ? o transmit analog ring output 29 tring3 ? o transmit analog ring output 4 tring4 ? o transmit analog ring output 99 ts0 ? i transceiver select 0 100 ts1 ? i transceiver select 1 81 tser1 ? i transmit serial data 56 tser2 ? i transmit serial data 31 tser3 ? i transmit serial data 6 tser4 ? i transmit serial data 82 tsync1 ? i/o transmit sync 57 tsync2 ? i/o transmit sync 32 tsync3 ? i/o transmit sync 7 tsync4 ? i/o transmit sync 76 ttip1 ? o transmit analog tip output 51 ttip2 ? o transmit analog tip output 26 ttip3 ? o transmit analog tip output 1 ttip4 ? o transmit analog tip output 78 tvdd1 ? ? transmit analog positive supply 53 tvdd2 ? ? transmit analog positive supply 28 tvdd3 ? ? transmit analog positive supply 3 tvdd4 ? ? transmit analog positive supply 77 tvss1 ? ? transmit analog signal ground 52 tvss2 ? ? transmit analog signal ground 27 tvss3 ? ? transmit analog signal ground 2 tvss4 ? ? transmit analog signal ground 74 wr (r / w ) sdi i write input (read/write) [serial data input] note: eqvss lines are wired to rvss lines.
ds21q59 quad e1 transceiver 10 of 76 table 4-b. pin assignments (sorted by number) name pin parallel port enabled serial port enabled type function [serial port mode in brackets] 1 ttip4 ? o transmit analog tip output 2 tvss4 ? ? transmit analog signal ground 3 tvdd4 ? ? transmit analog positive supply 4 tring4 ? o transmit analog ring output 5 tclk4 ? i transmit clock 6 tser4 ? i transmit serial data 7 tsync4 ? i/o transmit sync 8 dvss4 ? ? digital signal ground 9 dvdd4 ? ? digital positive supply 10 outb3 ? o user-selectable output b 11 outa3 ? o user-selectable output a 12 sysclk3 ? i transmit/receive system clock 13 rser3 ? o receive serial data 14 rsync3 ? i/o receive sync 15 rvss4 ? ? receive analog signal ground 16 rtip3 ? i receive analog tip input 17 rring3 ? i receive analog ring input 18 rvdd4 ? ? receive analog positive supply 19 d0/ad0 ? i/o data bus bit 0/address/data bus bit 0 20 d1/ad1 ? i/o data bus bit 1/address/data bus bit 1 21 d2/ad2 ? i/o data bus bit 2/address/data bus bit 2 22 d3/ad3 ? i/o data bus bit 3/address/data bus bit 3 23 d4/ad4 ? i/o data bus bit 4/address/data bus bit 4 24 d5/ad5 ? i/o data bus bit 5/address/data bus bit 5 25 d6/ad6 ? i/o data bus bit 6/address/data bus bit 6 26 ttip3 ? o transmit analog tip output 27 tvss3 ? ? transmit analog signal ground 28 tvdd3 ? ? transmit analog positive supply 29 tring3 ? o transmit analog ring output 30 tclk3 ? i transmit clock 31 tser3 ? i transmit serial data 32 tsync3 ? i/o transmit sync 33 dvss3 ? ? digital signal ground 34 dvdd3 ? ? digital positive supply 35 outb2 ? o user-selectable output b 36 outa2 ? o user-selectable output a 37 sysclk2 ? i transmit/receive system clock 38 rser2 ? o receive serial data 39 rsync2 ? i/o receive sync 40 rvss3 ? ? receive analog signal ground 41 rtip2 ? i receive analog tip input 42 rring2 ? i receive analog ring input 43 rvdd3 ? ? receive analog positive supply 44 d7/ad7 sdo i/o data bus bit 7/addres s/data bus bit 7 [serial data output] 45 a0 ices i address bus bit 0/serial port [input-clock edge select] 46 a1 oces i address bus bit 1/serial port [output-clock edge select] 47 a2 ? i address bus bit 2 48 a3 ? i address bus bit 3 49 a4 ? i address bus bit 4 50 ale (as)/a5 ? i address latch enable/address bus bit 5 51 ttip2 ? o transmit analog tip output 52 tvss2 ? ? transmit analog signal ground 53 tvdd2 ? ? transmit analog positive supply 54 tring2 ? o transmit analog ring output
ds21q59 quad e1 transceiver 11 of 76 name pin parallel port enabled serial port enabled type function [serial port mode in brackets] 55 tclk2 ? i transmit clock 56 tser2 ? i transmit serial data 57 tsync2 ? i/o transmit sync 58 dvss2 ? ? digital signal ground 59 dvdd2 ? ? digital positive supply 60 outb1 ? o user-selectable output b 61 outa1 ? o user-selectable output a 62 sysclk1 ? i transmit/receive system clock 63 rser1 ? o receive serial data 64 rsync1 ? i/o receive sync 65 rvss2 ? ? receive analog signal ground 66 rtip1 ? i receive analog tip input 67 rring1 ? i receive analog ring input 68 rvdd2 ? ? receive analog positive supply 69 ajacko ? o alternate jitter attenuator clock output 70 ajacki ? i alternate jitter attenuator clock input 71 4/8/16mck ? o 4.096mhz, 8.192mhz, or 16.384mhz clock 72 refclk ? i/o reference clock 73 mclk ? i master clock input 74 wr (r/ w ) sdi i write input (read/write) [serial data input] 75 rd ( ds ) sclk i read input (data strobe) [serial port clock] 76 ttip1 ? o transmit analog tip output 77 tvss1 ? ? transmit analog signal ground 78 tvdd1 ? ? transmit analog positive supply 79 tring1 ? o transmit analog ring output 80 tclk1 ? i transmit clock 81 tser1 ? i transmit serial data 82 tsync1 ? i/o transmit sync 83 dvss1 ? ? digital signal ground 84 dvdd1 ? ? digital positive supply 85 outb4 ? o user-selectable output b 86 outa4 ? o user-selectable output a 87 sysclk4 ? i transmit/receive system clock 88 rser4 ? o receive serial data 89 rsync4 ? i/o receive sync 90 rvss1 ? ? receive analog signal ground 91 rtip4 ? i receive analog tip input 92 rring4 ? i receive analog ring input 93 rvdd1 ? ? receive analog positive supply 94 int ? o interrupt 95 pbts ? i parallel bus type select 96 bts0 ? ? bus type select 0 97 bts1 ? ? bus type select 1 98 cs ? i chip select 99 ts0 ? i transceiver select 0 100 ts1 ? i transceiver select 1 note: eqvss lines are wired to rvss.
ds21q59 quad e1 transceiver 12 of 76 4.1 pin function descriptions table 4-c. system (backplane) interface pins name type function tclk i transmit clock. tclk is a 2.048mhz primary clock that is used to clock data through the transmit formatter. tser i transmit serial data. transmit nrz serial data. tser is sampled on the falling edge of tclk when ibo disabled. it is sampled on the falling edge of sysclk when the ibo function is enabled. tsync i/o transmit sync. as an input, pulse at this pin establishes either frame or multiframe boundaries for the transmitter. as an output, it can be programmed to output either a frame or multiframe pulse. rser o receive serial data. rser is the received nrz serial data. rser is updated on the rising edges of rclk when the receive elastic store is disabled. it is updated on the rising edges of sysclk when the receive elastic store is enabled. rsync i/o receive sync. an extracted pulse one rclk wide is output at this pin that identifies either frame or cas/crc4 multiframe boundaries. if the receive elastic store is enabled, this pin can be enabled to be an input at which a frame-boundary pulse synchronous with sysclk is applied. sysclk i system clock. sysclk is a 2.048mhz clock used to clock data out of the receive elastic store. when the ibo is enabled sysclk can be a 4.096mhz, 8.192mhz, or 16.384mhz clock. outa o user-selectable output a. outa is a multifunction pin the host can program to output various alarms, clocks, or data, or be used to control external circuitry. outb o user-selectable output b. outb is a multifunction pin the host can program to output various alarms, clocks, or data, or be used to control external circuitry. table 4-d. alternate jitter attenuator name type function ajacki i alternate jitter attenuator clock input. ajacki is clock input to the alternate jitter attenuator. ajacko o alternate jitter attenuator clock output. ajacko is clock output of the alternate jitter attenuator. table 4-e. clock synthesizer name type function 4/8/16mck o 4.096mhz/8.192mhz/16.384mhz clock output. 4/8/16mck is a 4.096mhz, 8.192mhz, or 16.384mhz clock output that is referenced to one of the four recovered line clocks (rclks) or to an external 2.048mhz reference. refclk i/o reference clock. refclk can be configured as an output to source a 2.048mhz reference clock or as an input to supply a 2.048mhz reference clock from an external source to the clock synthesizer. table 4-f. parallel port control pins name type function int o interrupt. int flags the host controller during conditions and change of conditions defined in status registers 1 and 2 and the hdlc status register. it is an active-low, open-drain output. bts0 i bus type select bit 0. bts0 is used with bts1 to select between muxed, nonmuxed, serial bus operation, and output high-z mode. bts1 i bus type select bit 1. bts1 is used with bts0 to select between muxed, nonmuxed, serial bus operation, and output high-z mode. ts0 i transceiver select bit 0. ts0 is used with ts1 to select one of four transceivers. ts1 i transceiver select bit 1. ts1 is used with ts0 to select one of four transceivers. pbts i parallel bus type select. pbts is used to select between motorola and intel parallel bus types. ad0 to ad7/sdo i/o data bus or address/data bus [d0 to d6], data bus or address/data bus [d7]/serial port output. in nonmultiplexed bus operation (mux = 0), these pins serve as the data bus. in multiplexed bus operation (mux = 1), they serve as an 8-bit multiplexed address/data bus. a0 to a4 i address bus. in nonmultiplexed bus operation, these pins serve as the address bus. in multiplexed bus operation, these pins are not used and should be wired low. rd ( ds )/sclk i read input?data strobe/serial port clock. rd and ds are active-low signals. ds is active high when in multiplexed mode (section 26 ). cs i chip select. cs must be low to read or write to the device. it is an active-low signal . ale (as)/a5 i address latch enable (address strobe) or a6. in nonmultiplexed bus operation, this pin serves as the upper address bit. in multiplexed bus operation, it demultiplexes the bus on a positive-going edge. wr (r/ w ) / sdi i write input (read/write)/serial port data input, active low
ds21q59 quad e1 transceiver 13 of 76 table 4-g. serial port control pins name type function sdo o serial port data output. data at this output can be updated on the rising or fa lling edge of sclk. sdi i serial port data input. data at this input can be sampled on the rising or fa lling edge of sclk. ices i input clock-edge select. ices is used to select which sclk clock edge samples data at sdi. oces i output clock-edge select. oces is used to select which sclk clock edge updates data at sdo. sclk i serial port clock. sclk is used to clock data into and out of the serial port. table 4-h. line interface pins name type function mclk i master clock input. a 2.048mhz (50ppm) clock source with ttl levels is applied at this pin. this clock is used internally for both clock/data recovery and for jitter attenuation. rtip and rring i receive tip and ring. rtip and rring are analog inputs for clock recovery circuitry. these pins connect through a 1:1 step-up transformer to the e1 line. see section 21 for details. ttip and tring o transmit tip and ring. ttip and tring are analog line-driver outputs. these pins connect through a 1:2 step-up transformer to the e1 line. see section 21 for details. table 4-i. supply pins name type function dvdd supply digital positive supply. 3.3v 5%. should be wired to the rvdd and tvdd pins. rvdd supply receive analog positive supply. 3.3v 5%. should be wired to the dvdd and tvdd pins. tvdd supply transmit analog positive supply. 3.3v 5%. should be wired to the rvdd and dvdd pins. dvss supply digital signal ground. 0v. should be wired to the rvss and tvss pins. rvss supply receive analog signal ground. 0v. should be wired to dvss and tvss. tvss supply transmit analog signal ground. 0v. should be wired to dvss and rvss. 5. functional description the analog ami/hdb3 waveform off the e1 line is transformer-coupled into the ds21q59?s rring and rtip pins. the device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive framer, where the digital serial stream is analyzed to locate the framing/multiframe pattern. the ds21q59 contains an active filter that reconstructs the analog-received signal for the nonlinear losses that occur in transmission. the device has a usable receive sensitivity of 0db to -43db, which allows the device to operate on cables over 2km in length. the receive framer locates fas frame and crc and cas multiframe boundaries as well as detects incoming alarms including carrier loss, loss of synchronization, ais, and remote alarm. if needed, the receive elastic store can be enabled to absorb the phase and frequency differences between the recovered e1 data stream and an asynchronous backplane clock, which is provided at the sysclk input. the clock applied at the sysclk input can be either a 2.048mhz/4.096mhz/8.192mhz or 16.384mhz clock. the transmit framer is independent of the receive framer in both the clock requirements and characteristics. the transmit formatter provides the necessary frame/multiframe data overhead for e1 transmission. note: this data sheet assumes a particular nomenclature of the e1 operating environment. in each 125 s frame, there are 32 8-bit time slots numbered 0 to 31. time slot 0 is transmitted first and received first. these 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. time slot 0 is identical to channel 1, time slot 1 is identical to channel 2, and so on. each time slot (or channel) is made up of eight bits that are numbered 1 to 8. bit number 1, msb, is transmitted first. bit number 8, the lsb, is transmitted last. the term ?locked? is used to refer to two clock signals that are phase-locked or frequency-locked or derived from a common clock (i.e., an 8.192mhz clock can be locked to a 2.048mhz clock if they share the same 8khz component).
ds21q59 quad e1 transceiver 14 of 76 6. host interface port the ds21q59 is controlled through either a nonmultiplexed bus, a multiplexed bus, or serial interface bus by an external microcontroller or microprocessor. the device can operate with either intel or motorola bus timing configurations. see table 6-a for a description of the bus configurations. motorola bus signals are listed in parentheses (). see the timing diagrams in the ac electrical characteristics in section 26 for more details. table 6-a. bus mode select pbts bts1 bts0 parallel port mode 0 0 0 intel multiplexed 0 0 1 intel nonmultiplexed 1 0 0 motorola multiplexed 1 0 1 motorola nonmultiplexed x 1 0 serial x 1 1 test (outputs high-z) 6.1 parallel port operation when using the parallel interface on the ds21q59 (bts1 = 0) the user has the option for either multiplexed bus operation (bts1 = 0, bts0 = 0) or nonmultiplexed bus operation (bts1 = 0, bts0 = 1). the ds21q59 can operate with either intel or motorola bus timing configurations. if the pbts pin is wired low, intel timing is selected; if wired high, motorola timing is selected. all motorola bus signals are listed in parentheses (). see the timing diagrams in section 26 for more details. 6.2 serial port operation setting the bts1 pin = 1 and bts0 pin = 0 enables the serial bus interface on the ds21q59. port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. see section 26 for the ac timing of the serial port. all serial port accesses are lsb first. see figure 6-1 , figure 6-2 , figure 6-3 , and figure 6-4 for more details. reading or writing to the internal registers requires writing one address/command byte prior to transferring register data. the first bit written (lsb) of the address/command byte specifies whether the access is a read (1) or a write (0). the next five bits identify the register address. the next bit is reserved and must be set to 0 for proper operation. the last bit (msb) of the address/command byte enables the burst mode when set to 1. the burst mode causes all registers to be consecutively written or read. all data transfers are initiated by driving the cs input low. when input-clock edge select (ices) is low, input data is latched on the rising edge of sclk; when ices is high, input data is latched on the falling edge of sclk. when output-clock edge select (oces) is low, data is output on the falling edge of sclk; when oces is high, data is output on the rising edge of sclk. data is held until the next falling or rising edge. all data transfers are terminated if the cs input transitions high. port control logic is disabled and sdo is tri-stated when cs is high. figure 6-1. serial port operation mode 1 ices = 1 (sample sdi on the falling edge of sclk) oces = 1 ( update sdo on the rising edge of sclk ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r/ w a0 a1 a2 a3 a4 a5 b d1 d2 d3 d4 d5 d6 sclk sdi sdo c s lsb msb d0 lsb d7 msb
ds21q59 quad e1 transceiver 15 of 76 figure 6-2. serial port operation mode 2 figure 6-3. serial port operation mode 3 figure 6-4. serial port operation mode 4 ices = 1 (sample sdi on the falling edge of sclk) oces = 0 (update sdo on the falling edge of sclk) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r/ w a0 a1 a2 a3 a4 a5 b d1 d2 d3 d4 d5 d6 sclk sdi sdo c s lsb msb d0 lsb d7 msb ices = 0 (sample sdi on the rising edge of sclk) oces = 0 (update sdo on the falling edge of sclk) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r/ w a0 a1 a2 a3 a4 a5 b d1 d2 d3 d4 d5 d6 sclk sdi sdo c s lsb msb d0 lsb d7 msb ices = 0 (sample sdi on the rising edge of sclk) oces = 1 (update sdo on the rising edge of sclk) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r/ w a0 a1 a2 a3 a4 a5 b d1 d2 d3 d4 d5 d6 sclk sdi sdo c s lsb msb d0 lsb d7 msb
ds21q59 quad e1 transceiver 16 of 76 7. register map table 7-a. register map (sorted by address) address r/w name function 00 r vcr1 bpv or code violation count 1 01 r vcr2 bpv or code violation count 2 02 r crccr1 crc4 error count 1 03 r crccr2 crc4 error count 2 04 r ebcr1 e-bit count 1/prbs error count 1 05 r ebcr2 e-bit count 2/prbs error count 2 06 r fascr1 fas error count 1 07 r fascr2 fas error count 2 08 r/w rir receive information 09 r ssr synchronizer status 0a r/w sr1 status 1 0b r/w sr2 status 2 0c ? ? unused 0d ? ? unused 0e ? ? unused 0f r idr device id (note 1) 10 r/w rcr receive control 11 r/w tcr transmit control 1 12 r/w ccr1 common control 1 13 r/w ccr2 common control 2 14 r/w ccr3 common control 3 15 r/w ccr4 common control 4 16 r/w ccr5 common control 5 17 r/w licr line interface control register 18 r/w imr1 interrupt mask 1 19 r/w imr2 interrupt mask 2 1a r/w outac output a control 1b r/w outbc output b control 1c r/w ibo interleave bus operation register 1d r/w scicr system clock-interface control register (note 1) 1e r/w test3 (set to 00h) test 2 (note 2) 1f r/w ccr7 common control 7 20 r/w taf transmit align frame 21 r/w tnaf transmit nonalign frame 22 r tds0m transmit ds0 monitor 23 r/w tidr transmit idle definition 24 r/w tir1 transmit idle 1 25 r/w tir2 transmit idle 2 26 r/w tir3 transmit idle 3 27 r/w tir4 transmit idle 4 28 r raf receive align frame 29 r rnaf receive nonalign frame 2a r rds0m receive ds0 monitor 2b r/w pclb1 per-channel loopback control 1 2c r/w pclb2 per-channel loopback control 2 2d r/w pclb3 per-channel loopback control 3 2e r/w pclb4 per-channel loopback control 4 2f r/w ccr6 common control 6 30 r/w sa1 signaling access register 1 31 r/w sa2 signaling access register 2 32 r/w sa3 signaling access register 3 33 r/w sa4 signaling access register 4 34 r/w sa5 signaling access register 5 35 r/w sa6 signaling access register 6 36 r/w sa7 signaling access register 7
ds21q59 quad e1 transceiver 17 of 76 address r/w name function 37 r/w sa8 signaling access register 8 38 r/w sa9 signaling access register 9 39 r/w sa10 signaling access register 10 3a r/w sa11 signaling access register 11 3b r/w sa12 signaling access register 12 3c r/w sa13 signaling access register 13 3d r/w sa14 signaling access register 14 3e r/w sa15 signaling access register 15 3f r/w sa16 signaling access register 16 note 1: the device id register and the system clock-interface control register exist in transceiver 1 only (ts0, ts1 = 0). note 2: only the factory uses the test register; this register must be cleared (set to all zeros) on power-up initialization to ensure proper operation. 8. control, id, and test registers the ds21q59 operation is configured through a set of nine control registers. typically, registers are only accessed when the system is first powered up. once the device has been initialized, the control registers only need to be accessed when there is a change in the system configurat ion. there is one receive control register (rcr), one transmit control register (t cr), and seven common control registers (ccr1 to ccr7). each of these registers is described in this section. address 0fh has a device identification register (idr). the four msbs of this read-only register are fixed to 1 0 0 1, indicating that a ds21q59 e1 quad transceiver is present. the lower 4 bits of the idr are used to identify the revision of the device. this register exists in transceiver 1 only (ts0, ts1 = 0). the factory in testing the ds21q59 uses the test register at addresses 1e. on power-up, the test register should be set to 00h for the ds21q59 to properly operate. register name: idr register description: device identification register register address: 0f hex bit # 7 6 5 4 3 2 1 0 name 1 0 0 1 id3 id2 id1 id0 name bit function 1 7 bit 7 0 6 bit 6 0 5 bit 5 1 4 bit 4 id3 3 chip revision bit 3. msb of a decimal code that represents the chip revision. id2 1 chip revision bit 2 id1 2 chip revision bit 1 id0 0 chip revision bit 0. lsb of a decimal code that represents the chip revision.
ds21q59 quad e1 transceiver 18 of 76 8.1 power-up sequence on power-up and after the supplies are stable, the ds21q59 should be configured for operation by writing to all the internal registers (this includes setting the test register to 00h) since the contents of the internal registers cannot be predicted on power-up. the lirst (ccr5.4) should be toggled from 0 to 1 to reset the line interface circuitry. (it takes the device about 40ms to recover from the lirst bit being toggled.) after the sysclk input is stable, the esr bits (ccr4.5 and ccr4.6) should be toggled from 0 to 1 (this step can be skipped if the elastic store is disabled). register name: rcr register description: receive control register register address: 10 hex bit # 7 6 5 4 3 2 1 0 name rsmf rsm rsio rese ? frc synce resync name bit function rsmf 7 rsync multiframe function. only used if the rsync pin is programmed in the multiframe mode (rcr.6 = 1). 0 = rsync outputs cas multiframe boundaries. 1 = rsync outputs crc4 multiframe boundaries. rsm 6 rsync mode select 0 = frame mode (see the timing diagrams in section 24.1 ) 1 = multiframe mode (see the timing diagrams in section 24.1 ) rsio 5 rsync i/o select. (note: this bit must be set to 0 when rcr .4 = 0.) 0 = rsync is an output (depends on rcr.6) 1 = rsync is an input (only valid if elastic store enabled) rese 4 receive elastic store enable 0 = elastic store is bypassed 1 = elastic store is enabled ? 3 unused. should be set = 0 for proper operation. frc 2 frame resync criteria 0 = resync if fas received in error three consecutive times 1 = resync if fas or bit 2 of non-fas is received in error three consecutive times synce 1 sync enable 0 = auto resync enabled 1 = auto resync disabled resync 0 resync. when toggled from low to high, a resync is initiated. must be cleared and set again for a subsequent resync.
ds21q59 quad e1 transceiver 19 of 76 table 8-a. sync/resync criteria frame or multiframe level sync criteria resync criteria itu spec. fas fas present in frame n and n + 2, and fas not present in frame n + 1 three consecutive incorrect fas received; alternate (rcr1.2 = 1): if the above criteria is met or three consecutive incorrect bit 2 of non-fas received g.706 4.1.1 4.1.2 crc4 two valid mf alignment words found within 8ms 915 or more crc4 codewords out of 1000 received in error g.706 4.2 and 4.3.2 cas valid mf alignment word found and previous time slot 16 contains code other than all zeros two consecutive mf alignment words received in error g.732 5.2 register name: tcr register description: transmit control register register address: 11 hex bit # 7 6 5 4 3 2 1 0 name ifss tfpt aebe tua1 tsis tsa1 tsm tsio name bit function ifss 7 internal frame-sync select 0 = tsync normal 1 = if tsync is in the input mode (tsio = 0), then tsync is internally replaced by the recovered receive frame sync. the tsync pin is ignored 1 = if tsync is in the output mode (tsio = 1), then tsync outputs the recovered multiframe frame sync tfpt 6 transmit time slot 0 pass through 0 = fas bits/sa bits/remote alarm sourced internally from the taf and tnaf registers 1 = fas bits/sa bits/remote alarm sourced from tser aebe 5 automatic e-bit enable 0 = e-bits not automatically set in the transmit direction 1 = e-bits automatically set in the transmit direction tua1 4 transmit unframed all ones 0 = transmit data normally 1 = transmit an unframed all-ones code tsis 3 transmit international bit select 0 = sample si bits at tser pin 1 = source si bits from taf and tnaf registers (in this mode, tcr.6 must be set to 0) tsa1 2 transmit signaling all ones 0 = normal operation 1 = force time slot 16 in every frame to all ones tsm 1 tsync mode select 0 = frame mode (see the timing diagrams in section 24.2 ) 1 = cas and crc4 multiframe mode (see the timing diagrams in section 24.2 ) tsio 0 tsync i/o select 0 = tsync is an input 1 = tsync is an output note: see figure 24-9 for more details about how the transmit control register affects ds21q59 operation.
ds21q59 quad e1 transceiver 20 of 76 register name: ccr1 register description: common control register 1 register address: 12 hex bit # 7 6 5 4 3 2 1 0 name flb thdb3 tibe tcrc4 rsms rhdb3 pclms rcrc4 name bit function flb 7 framer loopback. see section 8.2 for details. 0 = loopback disabled 1 = loopback enabled thdb3 6 transmit hdb3 enable 0 = hdb3 disabled 1 = hdb3 enabled tibe 5 transmit insert bit error. a 0-to-1 transition causes a single bit error to be inserted in the transmit path. tcrc4 4 transmit crc4 enable 0 = crc4 disabled 1 = crc4 enabled rsms 3 receive signaling mode select 0 = cas signaling mode. receiver searches for the cas mf alignment signal. 1 = ccs signaling mode. receiver does not search for the cas mf alignment signal. rhdb3 2 receive hdb3 enable 0 = hdb3 disabled 1 = hdb3 enabled pclms 1 per-channel loopback mode select. see section 17 for details. 0 = remote per-channel loopback 1 = local per-channel loopback rcrc4 0 receive crc4 enable 0 = crc4 disabled 1 = crc4 enabled
ds21q59 quad e1 transceiver 21 of 76 8.2 framer loopback when ccr1.7 is set to 1, the ds21q59 enters a framer loopback (flb) mode ( figure 3-1 ). this loopback is useful in testing and debugging applications. in flb mode, the sct loops data from the transmitter back to the receiver. when flb is enabled, the following occurs: 1) data is transmitted as normal at tposo and tnego. 2) data input through rposi and rnegi is ignored. 3) the rclk output is replaced with the tclk input. register name: ccr2 register description: common control register 2 register address: 13 hex bit # 7 6 5 4 3 2 1 0 name ecus vcrfs aais ara rserc lotcmc rcla tcss name bit function ecus 7 error counter update select. see section 10 for details. 0 = update error counters once a second 1 = update error counters every 62.5ms (500 frames) vcrfs 6 vcr function select. see section 10 for details. 0 = count bipolar violations (bpvs) 1 = count code violations (cvs) aais 5 automatic ais generation 0 = disabled 1 = enabled ara 4 automatic remote alarm generation 0 = disabled 1 = enabled rserc 3 rser control 0 = allow rser to output data as received under all conditions 1 = force rser to 1 under loss-of-frame alignment conditions lotcmc 2 loss-of-transmit clock mux control. determines whether the transmit formatter should switch to the ever present rclk if the tclk should fail to transition. 0 = do not switch to rclk if tclk stops 1 = switch to rclk if tclk stops rcla 1 receive carrier loss (rcl) alternate criteria 0 = rcl declared upon 255 consecutive 0s (125 s) 1 = rcl declared upon 2048 consecutive 0s (1ms) tcss 0 transmit clock source select. this function allows the user to internally select rclk as the clock source for the transmit formatter. 0 = source of transmit clock is determined by ccr2.2 (lotcmc) 1 = forces transmitter to internally switch to rclk as source of transmit clock; signal at tclk pin is ignored
ds21q59 quad e1 transceiver 22 of 76 8.3 automatic alarm generation the device can be programmed to automatically transmit ais or remote alarm. when automatic ais generation is enabled (ccr2.5 = 1), the device monitors the receive framer to determine if any of the following conditions are present: loss-of-receive frame synchronization, ais alarm (all ones) reception, or loss-of-receive carrier (or signal). if one (or more) of these conditions is present, the framer forces an ais alarm. when automatic rai generation is enabled (ccr2.4 = 1), the receiver is monitored to determine if any of the following conditions are present: loss-of-receive frame synchronization, ais alarm (all ones) reception, or loss-of- receive carrier (or signal), or if crc4 multiframe synchronization cannot be found within 128ms of fas synchronization (if crc4 is enabled). if one (or more) of these conditions is present, the device transmits an rai alarm. rai generation conforms to ets 300 011 specifications, and a constant remote alarm is transmitted if the ds21q59 cannot find crc4 multiframe synchronization within 400ms as per g.706. register name: ccr3 register description: common control register register address: 14 hex bit # 7 6 5 4 3 2 1 0 name rlb llb liais tcm4 tcm3 tcm2 tcm1 tcm0 name bit function rlb 7 remote loopback. see section 8.4 for details. 0 = loopback disabled 1 = loopback enabled llb 6 local loopback. see section 8.5 for details. 0 = loopback disabled 1 = loopback enabled liais 5 line interface ais-generation enable 0 = allow normal data to be transmitted at ttip and tring 1 = force unframed all ones to be transmitted at ttip and tring at the mclk rate tcm4 4 transmit channel monitor bit 4 . msb of a channel decode that determines which transmit channel data appears in the tds0m register. see section 10 or details. tcm3 3 transmit channel monitor bit 3 tcm2 2 transmit channel monitor bit 2 tcm1 1 transmit channel monitor bit 1 tcm0 0 transmit channel monitor bit 0. lsb of the channel decode. 8.4 remote loopback when ccr4.7 is set to 1, the ds21q59 is forced into remote loopback (rlb) mode. in this loopback, data input through the rposi and rnegi pins is transmitted back to the tposo and tnego pins. data continues to pass through the ds21q59?s receive framer as it would normally and the data from the transmit formatter is ignored ( figure 3-1 ).
ds21q59 quad e1 transceiver 23 of 76 8.5 local loopback when ccr4.6 is set to 1, the ds21q59 is forced into local loopback (llb) mode. in this loopback, data continues to be transmitted as normal. data being received at rtip and rring is replaced with the data being transmitted. data in this loopback passes through the jitter attenuator ( figure 3-1 ). register name: ccr4 register description: common control register 4 register address: 15 hex bit # 7 6 5 4 3 2 1 0 name lirst resa resr rcm4 rcm3 rcm2 rcm1 rcm0 name bit function lirst 7 line interface reset. setting this bit from 0 to 1 initiates an internal reset that affects the clock recovery state machine and jitter attenuator. normally this bit is only toggled on power-up. it must be cleared and set again for a subsequent reset. resa 6 receive elastic store align. setting this bit from 0 to 1 may force the receive elastic store?s write/read pointers to a minimum separation of half a frame. no action is taken if the pointer separation is already greater than or equal to half a frame. if pointer separation is less than half a frame, the command is executed and data is disrupted. this bit should be toggled after sysclk has been applied and is stable. it must be cleared and set again for a subsequent align. see section 18 for details. resr 5 receive elastic store reset. setting this bit from 0 to 1 forces the receive elastic store to a depth of one frame. receive data is lost during the reset. the bit should be toggled after sysclk has been applied and is stable. it must be cleared and set again for a subsequent reset. see section 18 for details. rcm4 4 receive channel monitor bit 4. msb of a channel decode that determines which receive channel data appears in the rds0m register. see section 10 for details. rcm3 3 receive channel monitor bit 3 rcm2 2 receive channel monitor bit 2 rcm1 1 receive channel monitor bit 1 rcm0 0 receive channel monitor bit 0. lsb of the channel decode.
ds21q59 quad e1 transceiver 24 of 76 register name: ccr5 register description: common control register 5 register address: 16 hex bit # 7 6 5 4 3 2 1 0 name liuodo cdig liusi irtsel tprbs1 tprbs0 rprbs1 rprbs0 name bit function liuodo 7 line interface open-drain option. this control bit determines whether or not the ttip and tring outputs are open drain. the line driver outputs can be forced open drain to allow 6v peak pulses to be generated or to allow the creation of a very low power interface. 0 = allow ttip and tring to operate normally 1 = force the ttip and tring outputs to be open drain cdig 6 customer disconnect indication generator. this control bit determines whether the line interface generates an unframed ...1010... pattern at ttip and tring instead of the normal data pattern. 0 = generate normal data at ttip and tring 1 = generate a ...1010... pattern at ttip and tring liusi 5 line interface g.703 synchronization interface enable. this control bit works with ccr7.0 to select g.703 functionality on the transmitter and receiver ( table 8-b ). these bits determine whether the line receiver and transmitter should receive/transmit a normal e1 signal (section 6 of g.703) or a 2.048mhz synchronization signal (section 10 of g.703). irtsel 4 receive termination select. this function applies internal parallel resistance to the normal 120 external termination to create a 75 termination. 0 = normal 120 external termination 1 = internally adjust receive termination to 75 tprbs1 3 transmit prbs mode bit 1 tprbs0 2 transmit prbs mode bit 0 rprbs1 1 receive prbs mode bit 1 rprbs0 0 receive prbs mode bit 0 table 8-b. g.703 function liusi (ccr5.5) tg703 (ccr7.0) function 0 0 transmit and receive function normally 0 1 transmit g.703 signal, receiver functions normally 1 0 transmit and receive g.703 signal 1 1 receive g.703, transmitter functions normally
ds21q59 quad e1 transceiver 25 of 76 register name: ccr6 register description: common control register 6 register address: 2f hex bit # 7 6 5 4 3 2 1 0 name otm1 otm0 sras ltc/sc t16s ? ? reset name bit function otm1 7 output test mode 1 ( table 8-c ) otm0 6 output test mode 0 ( table 8-c ) sras 5 signaling read access select. this bit controls the function of registers sa1 through sa16 when reading. 0 = reading sa1?sa16 accesses receive signaling data 1 = reading sa1?sa16 accesses transmit signaling data ltc/sc 4 loss-of-transmit clock/signaling change-of-state select. this bit determines how the status register bit at sr2.2 operates. 0 = sr2.2 indicates loss-of-transmit clock 1 = sr2.2 indicates signaling data has changed states since the last multiframe t16s 3 time slot 16 select . transmit signaling insertion enable. 0 = signaling is not inserted into the transmit path from sa1?sa16 1 = signaling is inserted into the transmit path from sa1?sa16 ? 2 unused. should be set = 0 for proper operation. ? 1 unused. should be set = 0 for proper operation. reset 0 reset . a low-to-high transition of this bit resets all register bits to 0. table 8-c. output modes otm1 otm0 outputs 0 0 normal operation 0 1 outputs in tri-state 1 0 outputs low 1 1 outputs high
ds21q59 quad e1 transceiver 26 of 76 register name: ccr7 register description: common control register 7 register address: 1f hex bit: 7 6 5 4 3 2 1 0 name: ? ? ? ? 136s alb ? tg703 name bit function ? 7 unused. should be set = 0 for proper operation. ? 6 unused. should be set = 0 for proper operation. ? 5 unused. should be set = 0 for proper operation. ? 4 unused. should be set = 0 for proper operation. 136s 3 1:1.36 transformer select 0 = 1:2 transmit transformer 1 = 1:1.36 or 1:1.6 transmit transformer (see table below for details) alb 2 analog loopback. setting this bit internally connects ttip and tring to rtip and rring. the external signal at the rtip and rring pins is ignored. ? 1 unused. should be set = 0 for proper operation. tg703 0 transmit g.703. this control bit works with ccr5.5 to select g.703 functionality on the transmitter and receiver ( table 8-b ). these bits determine whether the line receiver and transmitter should receive/ transmit a normal e1 signal (section 6 of g.703) or a 2.048mhz synchronization signal (section 10 of g.703). 136s l2 l1 l0 application transformer 1:1.6 transformer 1:1.36 1 0 0 0 75 rt = 0 n.m. 1 0 0 1 120 rt = 0 n.m. 1 0 1 0 75 rt = 2.7 rt = 0 1 0 1 1 120 rt = 3.3 rt = 0 1 1 0 0 n.m. n.m. n.m. 1 1 0 1 n.m. n.m. n.m. 1 1 1 0 n.m. n.m. n.m. 1 1 1 1 n.m. n.m. n.m. n.m. = not meaningful
ds21q59 quad e1 transceiver 27 of 76 9. status and information registers the ds21q59 has a set of four registers that contain information about a framer?s real-time status. the registers include status register 1 (sr1), status register 2 (sr2), receive information register (rir), and synchronizer status register (ssr). when a particular event has occurred (or is occurring), the appropriate bit in one of these four registers is set to 1. all the bits in the sr1, sr2, and rir1 registers operate in a latched fashion. the ssr contents are not latched, which means that if an event or an alarm occurs and a bit is set to 1 in any of the registers, the bit remains set until the user reads that bit. the bit is cleared when it is read and is not set again until the event has occurred again (or, in the case of the rua1, rra, rcl, and rlos alarms, the bit remains set if the alarm is still present). the user always precedes a read of the sr1, sr2, and rir registers with a write. the byte written to the register informs the framer which bits the user wishes to read and have cleared. the user writes a byte to one of these registers with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. when a 1 is written to a bit location, the read register updates with the latest information. when a 0 is written to a bit position, the read register does not update and the previous value is held. a write to the status and information registers is immediately followed by a read of the same register. the read result should be logically anded with the mask byte that was just written, and this value should be written back into the same register to ensure the bit clears. this second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access through the parallel port. this write-read-write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. this operation is key in controlling the ds21q59 with higher-order software languages. the ssr register operates differently than the other three. it is a read-only register and reports the status of the synchronizer in real time. this register is not latched and it is not necessary to precede a read of this register with a write. the sr1 and sr2 registers have the unique ability to initiate a hardware interrupt through the int output pin. each of the alarms and events in sr1 and sr2 can be either masked or unmasked from the interrupt pin through interrupt mask register 1 (imr1) and interrupt mask register 2 (imr2). the interrupts caused by alarms in sr1 (rua1, rra, rcl, and rlos) act differently than the interrupts caused by events in sr1 and sr2 (rsa1, rdma, rsa0, rslip, rmf, tmf, sec, taf, lotc, and rcmf). the alarm- caused interrupts force the int pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in table 9-a ). the int pin is allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur, even if the alarm is still present. the event-based interrupts force the int pin low when the event occurs. the int pin returns high () when the user reads the event bit that caused the interrupt to occur. furthermore, some event-based interrupts occur continuously as long as the event is occurring (rslip, sec, tmf, rmf, taf, raf, rcmf). other event-based interrupts force the int pin low only once when the event is first detected (lotc, prsbd, rdma, rsa1, rsa0), that is, the prbsd interrupt fires once when the receiver detects the prbs pattern. if the receiver continues to receive the prbs pattern, no more interrupts are fired. if the receiver then detects that prbs is no longer being sent, it resets and, when it receives the prbs pattern again, another interrupt is fired.
ds21q59 quad e1 transceiver 28 of 76 9.1 interrupt handling the host can quickly determine which status registers in the four ports are causing an interrupt by reading one of the unused addresses such as 0ch, 0dh, or 0eh in any port. bit # 7 6 5 4 3 2 1 0 name sr2p4 sr1p4 sr2p3 sr1p3 sr2p2 sr1p2 sr2p1 sr1p1 name bit function sr2p4 7 status register 2, port 4. a 1 in this bit position indicates that status register 2 in port 4 is asserting an interrupt. sr1p4 6 status register 1, port 4. a 1 in this bit position indicates that status register 1 in port 4 is asserting an interrupt. sr2p3 5 status register 2, port 3. a 1 in this bit position indicates that status register 2 in port 3 is asserting an interrupt. sr1p3 4 status register 1, port 3. a 1 in this bit position indicates that status register 1 in port 3 is asserting an interrupt. sr2p2 3 status register 2, port 2. a 1 in this bit position indicates that status register 2 in port 2 is asserting an interrupt. sr1p2 2 status register 1, port 2. a 1 in this bit position indicates that status register 1 in port 2 is asserting an interrupt. sr2p1 1 status register 2, port 1. a 1 in this bit position indicates that status register 2 in port 1 is asserting an interrupt. sr1p1 0 status register 1, port 1. a 1 in this bit position indicates that status register 1 in port 1 is asserting an interrupt. register name: rir register description: receive information register register address: 08 hex bit # 7 6 5 4 3 2 1 0 name rgm1 rgm0 jalt resf rese crcrc fasrc casrc name bit function rgm1 7 receive gain monitor bit 1. see table below for level indication. rgm0 6 receive gain monitor bit 0. see table below for level indication. jalt 5 jitter attenuator limit trip . set when the jitter attenuator fifo reaches to within 4 bits of its limit; useful for debugging jitter attenuation operation. resf 4 receive elastic store full. set when the receive elastic store buffer fills and a frame is deleted. rese 3 receive elastic store empty. set when the receive elastic store buffer empties and a frame is repeated. crcrc 2 crc resync criteria met. set when 915/1000 codewords are received in error. fasrc 1 fas resync criteria met. set when three consecutive fas words are received in error. casrc 0 cas resync criteria met. set when two consecutive cas mf alignment words are received in error. level indication rgm1 rgm0 level (db) 0 0 0 to 10 0 1 10 to 20 1 0 20 to 30 1 1 >30
ds21q59 quad e1 transceiver 29 of 76 register name: ssr register description: synchronizer status register register address: 09 hex bit # 7 6 5 4 3 2 1 0 name csc5 csc4 csc3 csc2 csc0 fassa cassa crc4sa name bit function csc5 7 crc4 sync counter bit 5. msb of the 6-bit counter. csc4 6 crc4 sync counter bit 4 csc3 5 crc4 sync counter bit 3 csc2 4 crc4 sync counter bit 2 csc0 3 crc4 sync counter bit 0. lsb of the 6-bit counter. counter bit 1 is not accessible. fassa 2 fas sync active. set while the synchronizer is searching for alignment at the fas level. cassa 1 cas mf sync active. set while the synchronizer is searching for the cas mf alignment word. crc4sa 0 crc4 mf sync active. set while the synchronizer is searching for the crc4 mf alignment word. 9.2 crc4 sync counter the crc4 sync counter increments each time the 8ms crc4 multiframe search times out. the counter is cleared when the framer has successfully obtained synchronization at the crc4 level. the counter can also be cleared by disabling the crc4 mode (ccr1.0 = 0). this counter is useful for determining the amount of time the framer has been searching for synchronization at the crc4 level. itu g.706 suggests that if synchronization at the crc4 level cannot be obtained within 400ms, the search s hould be abandoned and proper action taken. the crc4 sync counter rolls over. table 9-a. alarm criteria alarm set criteria clear criteria itu spec rsa1 (receive signaling all ones) over 16 consecutive frames (one full mf) time slot 16 contains less than three zeros over 16 consecutive frames (one full mf) time slot 16 contains three or more zeros g.732 4.2 rsa0 (receive signaling all zeros) over 16 consecutive frames (one full mf) time slot 16 contains all zeros over 16 consecutive frames (one full mf) time slot 16 contains at least a single one g.732 5.2 rdma (receive distant multiframe alarm) bit 6 in time slot 16 of frame 0 set to one for two consecutive mf bit 6 in time slot 16 of frame 0 set to zero for two consecutive mf o.162 2.1.5 rua1 (receive unframed all ones) fewer than three zeros in two frames (512 bits) more than two zeros in two frames (512 bits) o.162 1.6.1.2 rra (receive remote alarm) bit 3 of nonalign frame set to one for three consecutive occasions bit 3 of nonalign frame set to zero for three consecutive occasions o.162 2.1.4 rcl (receive carrier loss) 255 (or 2048) consecutive zeros received in 255-bit times at least 32 ones are received g.775/ g.962
ds21q59 quad e1 transceiver 30 of 76 register name: sr1 register description: status register 1 register address: 0a hex bit # 7 6 5 4 3 2 1 0 name rsa1 rdma rsa0 rslip rua1 rra rcl rlos name bit function rsa1 7 receive signaling all ones. set when the contents of time slot 16 contains fewer than three zeros over 16 consecutive frames. this alarm is not disabled in the ccs signaling mode. both rsa1 and rsa0 are set if a change in signaling is detected. rdma 6 receive distant mf alarm. set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. this alarm is not disabled in the ccs signaling mode. rsa0 5 receive signaling all zeros. set when over a full mf, time slot 16 contains all zeros. both rsa1 and rsa0 are set if a change in signaling is detected. rslip 4 receive elastic store slip. set when the elastic store has either repeated or deleted a frame of data. rua1 3 receive unframed all ones. set when an unframed all-ones code is received at rposi and rnegi. rra 2 receive remote alarm. set when a remote alarm is received at rposi and rnegi. rcl 1 receive carrier loss. set when 255 (or 2048 if ccr2.1 = 1) consecutive zeros have been detected at rtip and rring. (note: a receiver carrier loss based on data received at rposi and rnegi is available in the hsr register.) rlos 0 receive loss of sync. set when the device is not synchronized to the receive e1 stream.
ds21q59 quad e1 transceiver 31 of 76 register name: imr1 register description: interrupt mask register 1 register address: 18 hex bit # 7 6 5 4 3 2 1 0 name rsa1 rdma rsa0 rslip rua1 rra rcl rlos name bit function rsa1 7 receive signaling all ones 0 = interrupt masked 1 = interrupt enabled rdma 6 receive distant mf alarm 0 = interrupt masked 1 = interrupt enabled rsa0 5 receive signaling all zeros 0 = interrupt masked 1 = interrupt enabled rslip 4 receive elastic store slip occurrence 0 = interrupt masked 1 = interrupt enabled rua1 3 receive unframed all ones 0 = interrupt masked 1 = interrupt enabled rra 2 receive remote alarm 0 = interrupt masked 1 = interrupt enabled rcl 1 receive carrier loss 0 = interrupt masked 1 = interrupt enabled rlos 0 receive loss of sync 0 = interrupt masked 1 = interrupt enabled
ds21q59 quad e1 transceiver 32 of 76 register name: sr2 register description: status register 2 register address: 0b hex bit # 7 6 5 4 3 2 1 0 name rmf raf tmf sec taf lotc rcmf prbsd name bit function rmf 7 receive cas multiframe . set every 2ms (regardless if cas signaling is enabled or not) on receive multiframe boundaries. raf 6 receive align frame. set every 250s at the beginning of align frames. used to alert the host that si and sa bits are available in the raf and rnaf registers. tmf 5 transmit multiframe. set every 2ms (regardless if crc4 is enabled) on transmit multiframe boundaries. sec 4 one-second timer. set on increments of one second based on rclk. if ccr2.7 = 1, this bit is set every 62.5ms instead of once a second. taf 3 transmit align frame. set every 250s at the beginning of align frames. used to alert the host that the taf and tnaf registers need to be updated. lotc 2 loss-of-transmit clock. set when the tclk pin has not transitioned for one channel time (or 3.9ms). rcmf 1 receive crc4 multiframe. set on crc4 multiframe boundaries; continues to be set every 2ms on an arbitrary boundary if crc4 is disabled. prbsd 0 pseudorandom bit-sequence detect. when receive prbs is enabled, this bit is set when the 2 15 - 1 prbs pattern is detected at rpos and rneg. the prbs pattern can be framed, unframed, or in a specific time slot.
ds21q59 quad e1 transceiver 33 of 76 register name: imr2 register description: interrupt mask register 2 register address: 19 hex bit # 7 6 5 4 3 2 1 0 name rmf raf tmf sec taf lotc rcmf prbsd name bit function rmf 7 receive cas multiframe 0 = interrupt masked 1 = interrupt enabled raf 6 receive align frame 0 = interrupt masked 1 = interrupt enabled tmf 5 transmit multiframe 0 = interrupt masked 1 = interrupt enabled sec 4 one-second timer 0 = interrupt masked 1 = interrupt enabled taf 3 transmit align frame 0 = interrupt masked 1 = interrupt enabled lotc 2 loss-of-transmit clock 0 = interrupt masked 1 = interrupt enabled rcmf 1 receive crc4 multiframe 0 = interrupt masked 1 = interrupt enabled prbsd 0 pseudorandom bit-sequence detect 0 = interrupt masked 1 = interrupt enabled
ds21q59 quad e1 transceiver 34 of 76 10. error count registers each ds21q59 transceiver contains a set of four counters that record bipolar (bpvs) or code violations (cvs), errors in the crc4 smf codewords, e bits as reported by the far end, and word errors in the fas. the e-bit counter is reconfigured for counting errors in the prbs pattern if receive prbs is enabled. each of these four counters is automatically updated on either one-second boundaries (ccr2.70 = 0) or every 62.5ms (ccr2.7 = 1) as determined by the timer in status register 2 (sr2.4). hence, these registers contain performance data from either the previous second or the previous 62.5ms. the user can use the interrupt from the one-second timer to determine when to read these registers. the user has a full second (or 62.5ms) to read the counters before the data is lost. the counters saturate at their respective maximum counts and do not roll over. 10.1 bpv or cv counter violation count register 1 (vcr1) is the most significant word and vcr2 is the least significant word of a 16-bit counter that records either bpvs or cvs. if ccr2.6 = 0, the vcr counts bpvs. bpvs are defined as consecutive marks of the same polarity. in this mode, if the hdb3 mode is set for the receiver through ccr1.2, then hdb3 codewords are not counted as bpvs. if ccr2.6 = 1, the vcr counts cvs as defined in itu o.161. cvs are defined as consecutive bpvs of the same polarity. in most applications, the framer should be programmed to count bpvs when receiving ami code and to count cvs when receiving hdb3 code. this counter increments at all times and is not disabled by loss-of-sync conditions. the counter saturates at 65,535 and does not roll over. the bit-error rate on an e1 line would have to be greater than 10 -2 before the vcr would saturate. register name: vcr1, vcr2 register description: bipolar violation count registers register address: 00 hex, 01 hex bit # 7 6 5 4 3 2 1 0 v15 v14 v13 v12 v11 v10 v9 v8 name v7 v6 v5 v4 v3 v2 v1 v0 name bit function v15 vcr1.7 msb of the 16-bit code violation count. v0 vcr2.0 lsb of the 16-bit code violation count. 10.2 crc4 error counter crc4 count register 1 (crccr1) is the most significant word and crccr2 is the least significant word of a 16-bit counter that records word errors in the cyclic redundancy check 4 (crc4). since the maximum crc4 count in a one-second period is 1000, this counter cannot saturate. the counter is disabled during loss of sync at either the fas or crc4 level; it continues to count if loss-of-multiframe sync occurs at the cas level. crccr1 and crccr2 have an alternate function. register name: crccr1, crccr2 register description: crc4 count registers register address: 02 hex, 03 hex bit # 7 6 5 4 3 2 1 0 crc15 crc14 crc13 crc12 crc11 crc10 crc9 crc8 name crc7 crc6 crc5 crc4 crc/3 crc2 crc1 crc0 name bit function crc15 crccr1.7 msb of the 16-bit crc4 error count. crc0 crccr2.0 lsb of the 16-bit crc4 error count.
ds21q59 quad e1 transceiver 35 of 76 10.3 e-bit/prbs bit-error counter e-bit count register 1 (ebcr1) is the most significant word and ebcr2 is the least significant word of a 16-bit counter that records far-end block errors (febe) as reported in the first bit of frames 13 and 15 on e1 lines running with crc4 multiframe. these error count registers increment once each time the received e-bit is set to 0. since the maximum e-bit count in a one-second period is 1000, this counter cannot saturate. the counter is disabled during loss of sync at either the fas or crc4 level; it continues to count if loss-of-multiframe sync occurs at the cas level. alternately, this counter counts bit errors in the received prbs pattern when the receive prbs function is enabled. in this mode, the counter is active when the receive prbs detector can synchronize to the prbs pattern. this pattern can be framed, unframed, or in any time slot. see section 13 for more details. register name: ebcr1, ebcr2 register description: e-bit count registers register address: 04 hex, 05 hex bit # 7 6 5 4 3 2 1 0 eb15 eb14 eb13 eb12 eb11 eb10 eb9 eb8 name eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 name bit function eb15 ebcr1.7 msb of the 16-bit e-bit error count. eb0 ebcr2.0 lsb of the 16-bit e-bit error count. 10.4 fas error counter fas count register 1 (fascr1) is the most significant word and fascr2 is the least significant word of a 16-bit counter that records word errors in the fas in time slot 0. this counter is disabled when rlos is high. fas errors are not counted when the framer is searching for fas ali gnment and/or synchronization at either the cas or crc4 multiframe level. since the maximum fas word error count in a one-second period is 4000, this counter cannot saturate. register name: fascr1, fascr2 register description: fas error count registers register address: 06 hex, 07 hex bit # 7 6 5 4 3 2 1 0 fas15 fas14 fas13 fas12 fas11 fas10 fas9 fas8 name fas7 fas6 fas5 fas4 fas3 fas2 fas1 fas0 name bit function fas15 fascr1.7 msb of the 16-bit fas error count. fas0 fascr2.0 lsb of the 16-bit fas error count.
ds21q59 quad e1 transceiver 36 of 76 11. signaling operation registers sa1 and sa16 are used to access the transmit and receive signaling function. normally, reading these registers accesses the receive signaling data and writing these registers sources signaling data for the transmitter. the user can read what was written to the transmit signaling buffer by setting ccr6.5 = 1, then reading sa1?sa16. in most applications, however, ccr6.5 should be set = 0. 11.1 receive signaling signaling data is sampled from time slot 16 in the receive data stream and copied into the receive signaling buffers. the host can access the signaling data by reading sa1 through sa16. the signaling information in these registers is always updated on multiframe boundaries. the sr2.7 bit in status register 2 can be used to alert the host that new signaling data is present in the receive signaling buffers. the host has 2ms to read the signaling buffers before they are updated. 11.2 transmit signaling insertion of signaling data from the transmit signaling buffers is enabled by setting ccr6.3 = 1. signaling data is loaded into the transmit signaling buffers by writing the signaling data to sa1?sa16. on multiframe boundaries, the contents of the transmit signaling buffer is loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. the user can use the transmit multiframe interrupt in status register 2 (sr2.5) to know when to update the signaling bits. the host has 2ms to update the signaling data. the user only needs to update the signaling data that has changed since the last update. 11.3 cas operation for cas mode, the user must provide the cas alignment pattern (four 0s in the upper nibble of ts16). typically this is done by setting the upper four bits of sa1 = 0. the lower four bits are alarm bits. the user only needs to update the appropriate channel associated signaling data in sa2?sa16 on multiframe boundaries. register name: sa1 to sa16 register description: signaling registers register address: 30h to 3fh (msb) (lsb) 0 0 0 0 x y x x sa1 ch1-a ch1-b ch1-c ch1-d ch16- a ch16-b ch16-c ch16-d sa2 ch2-a ch2-b ch2-c ch2-d ch17- a ch17-b ch17-c ch17-d sa3 ch3-a ch3-b ch3-c ch3-d ch18- a ch18-b ch18-c ch18-d sa4 ch4-a ch4-b ch4-c ch4-d ch19- a ch19-b ch19-c ch19-d sa5 ch5-a ch5-b ch5-c ch5-d ch20- a ch20-b ch20-c ch20-d sa6 ch6-a ch6-b ch6-c ch6-d ch 21-a ch21-b ch21-c ch21-d sa7 ch7-a ch7-b ch7-c ch7-d ch22- a ch22-b ch22-c ch22-d sa8 ch8-a ch8-b ch8-c ch8-d ch23- a ch23-b ch23-c ch23-d sa9 ch9-a ch9-b ch9-c ch9-d ch24- a ch24-b ch24-c ch24-d sa10 ch10-a ch10-b ch10-c ch10-d ch25-a ch25-b ch25-c ch25-d sa11 ch11-a ch11-b ch11-c ch11-d ch26-a ch26-b ch26-c ch26-d sa12 ch12-a ch12-b ch12-c ch12-d ch27-a ch27-b ch27-c ch27-d sa13 ch13-a ch13-b ch13-c ch13-d ch28-a ch28-b ch28-c ch28-d sa14 ch14-a ch14-b ch14-c ch14-d ch29-a ch29-b ch29-c ch29-d sa15 ch15-a ch15-b ch15-c ch15-d ch30-a ch30-b ch30-c ch30-d sa16
ds21q59 quad e1 transceiver 37 of 76 12. ds0 monitoring function each ds21q59 framer can monitor one ds0 (64kbps) channel in the transmit direction and one ds0 channel in the receive direction at the same time. in the transmit direction, the user determines which channel is to be monitored by properly setting the tcm0 to tcm4 bits in the ccr3 register. in the receive direction, the rcm0 to rcm4 bits in the ccr4 register need to be properly set. the ds0 channel pointed to by the tcm0 to tcm4 bits appear in the transmit ds0 monitor (tds0m) register and the ds0 channel pointed to by the rcm0 to rcm4 bits appear in the receive ds0 (rds0m) register. the tcm4 to tcm0 and rcm4 to rcm0 bits should be programmed with the decimal decode of the appropriate e1 channel. for example, if ds0 channel 6 in the transmit direction and ds0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into ccr4 and ccr5: tcm4 = 0 rcm4 = 0 tcm3 = 0 rcm3 = 1 tcm2 = 1 rcm2 = 1 tcm1 = 0 rcm1 = 1 tcm0 = 1 rcm0 = 0 register name: ccr3 (repeated here from section 6 for convenience.) register description: common control register 3 register address: 14 hex bit # 7 6 5 4 3 2 1 0 name rlb llb liais tcm4 tcm3 tcm2 tcm1 tcm0 name bit function rlb 7 remote loopback llb 6 local loopback liais 5 line interface ais generation enable tcm4 4 transmit channel monitor bit 4 . msb of a channel decode that determines which transmit channel data appears in the tds0m register. see section 10 or details. tcm3 3 transmit channel monitor bit 3 tcm2 2 transmit channel monitor bit 2 tcm1 1 transmit channel monitor bit 1 tcm0 0 transmit channel monitor bit 0. lsb of the channel decode. register name: tds0m register description: transmit ds0 monitor register register address: 22 hex bit # 7 6 5 4 3 2 1 0 name b1 b2 b3 b4 b5 b6 b7 b8 name bit function b1 7 transmit ds0 channel bit 1. msb of the ds0 channel (first bit to be transmitted). b2 6 transmit ds0 channel bit 2 b3 5 transmit ds0 channel bit 3 b4 4 transmit ds0 channel bit 4 b5 3 transmit ds0 channel bit 5 b6 2 transmit ds0 channel bit 6 b7 1 transmit ds0 channel bit 7 b8 0 transmit ds0 channel bit 8. lsb of the ds0 channel (last bit to be transmitted).
ds21q59 quad e1 transceiver 38 of 76 register name: ccr4 (repeated here from section 6 for convenience.) register description: common control register 4 register address: 15 hex bit # 7 6 5 4 3 2 1 0 name lirst resa resr rcm4 rcm3 rcm2 rcm1 rcm0 name bit function lirst 7 line interface reset resa 6 receive elastic store align resr 5 receive elastic store reset rcm4 4 receive channel monitor bit 4. msb of a channel decode that determines which receive channel data appears in the rds0m register. see section 10 for details. rcm3 3 receive channel monitor bit 3 rcm2 2 receive channel monitor bit 2 rcm1 1 receive channel monitor bit 1 rcm0 0 receive channel monitor bit 0. lsb of the channel decode. register name: rds0m register description: receive ds0 monitor register register address: 2a hex bit # 7 6 5 4 3 2 1 0 name b1 b2 b3 b4 b5 b6 b7 b8 name bit function b1 7 receive ds0 channel bit 1. msb of the ds0 channel (first bit received). b2 6 receive ds0 channel bit 2 b3 5 receive ds0 channel bit 3 b4 4 receive ds0 channel bit 4 b5 3 receive ds0 channel bit 5 b6 2 receive ds0 channel bit 6 b7 1 receive ds0 channel bit 7 b8 0 receive ds0 channel bit 8. lsb of the ds0 channel (last bit received).
ds21q59 quad e1 transceiver 39 of 76 13. prbs generation and detection the ds21q59 can transmit and receive the 2 15 - 1 prbs pattern. this prbs pattern complies with itu-t o.151 specifications. the prbs pattern can be unframed (in all 256 bits of the frame), framed (in all time slots except ts0), or in any single time slot. register ccr5 contains the control bits for configuring the transmit and receives prbs functions. see table 13-a and table 13-b for selecting the transmit and receive modes of operation. in transmit and receive mode 1 operation, the transmit- and re ceive-channel monitor-select bits of registers ccr3 and ccr4 have an alternate use. when this mode is selected, these bits determine which time slot transmits and/or receives the prbs pattern. sr2.0 indicates when the receiver has synchronized to the prbs pattern. the prbs synchronizer remains in sync until it experiences six or more bit errors within a 64-bit span. choosing any receive mode other than normal causes the 16-bit e-bit error counter?ebcr1 and ebcr2?to be reconfigured for counting prbs errors. user-definable outputs outa or outb can be configured to output a pulse for every bit error received. see section 20 and table 20-a for details. this signal can be used with external circuitry to keep track of bit-error rates during prbs testing. once synchronized, any bit errors received cause a positive-going pulse, synchronous with rclk. table 13-a. transmit prbs mode select tprbs1 (ccr5.3) tpbrs0 (ccr5.2) mode 0 0 mode 0: normal (prbs disabled) 0 1 mode 1: prbs in tsx. prbs pattern is transmitted in a single time slot (ts). in this mode, the transmit-channel monitor-select bits in register ccr3 are used to select a time slot in which to transmit the prbs pattern. 1 0 mode 2: prbs in all but ts0. prbs pattern is transmitted in time slots 1 through 31. 1 1 mode 3: prbs unframed. prbs pattern is transmitted in all time slots. table 13-b. receive prbs mode select rprbs1 (ccr5.1) rpbrs0 (ccr5.0) mode 0 0 mode 0: normal (prbs disabled) 0 1 mode 1: prbs in tsx. prbs pattern is received in a single time slot (ts). in this mode, the receive-channel monitor-select bits in register ccr4 are used to select a time slot in which to receive the prbs pattern. 1 0 mode 2: prbs in all but ts0. prbs pattern is received in time slots 1 through 31. 1 1 mode 3: prbs unframed. prbs pattern is received in all time slots.
ds21q59 quad e1 transceiver 40 of 76 14. system clock interface a single system clock interface (sci) is common to all four ds21q59 transceivers. the sci is designed to allow any one of the four receivers to act as the master reference clock for the system. when multiple ds21q59s are used to build an n port system, the sci allows any one of the n ports to be the master. the selected reference is then distributed to the other ds21q59s through the refclk pin. the refclk pin acts as an output on the ds21q59, which has been selected to provide the reference clock from one of its four receivers. on ds21q59s not selected to source the reference clock, this pin becomes an input by writing 0s to the scsx bits. the reference clock is also passed to the clock synthesizer pll to generate a 2.048mhz, 4.096mhz, 8.192mhz, or 16.384mhz clock. this clock can then be used with the ibo function to merge up to eight e1 lines onto a single high-speed pcm bus. in the event that the master e1 port fails (enters a receive carrier loss condition), that port automatically switches to the clock present on the mclk pin. therefore, mclk acts as the backup source of master clock. the host can then find and select a functioning e1 port as the master. because the selected port?s clock is passed to the other ds21q59s in a multiple device configuration, one ds21q59?s synthesizer can always be the source of the high-speed clock. this allows smooth transitions when clock-source switching occurs. the sci control register exists in transceiver 1 only (ts0, ts1 = 0). register name: scicr register description: system clock interface control register (note: this register is valid only for transceiver 1 (ts0 = 0, ts1 = 0).) register address: 1d hex bit # 7 6 5 4 3 2 1 0 name ajacke bucs soe css1 css0 scs2 scs1 scs0 name bit function ajacke 7 ajack enable. this bit enables the alternate jitter attenuator. bucs 6 backup clock select. selects which clock source to switch to automatically during a loss-of-transmit clock event. 0 = during an lotc event switch to mclk 1 = during an lotc event switch to system reference clock soe 5 synthesizer output enable 0 = 2/4/8/16mck pin in high-z mode 1 = 2/4/8/16mck pin active css1 4 clock synthesizer select bit 1 ( table 14-a ) css0 3 clock synthesizer select bit 0 ( table 14-a ) scs2 2 system clock select bit 2 ( table 14-b ) scs1 1 system clock select bit 1 ( table 14-b ) scs0 0 system clock select bit 0 ( table 14-b ) table 14-a. synthesi zer output select css1 css0 synthesizer output frequency (mhz) 0 0 2.048 0 1 4.096 1 0 8.192 1 1 16.384 table 14-b. system clock selection scs2 scs1 scs0 port selected as master 0 0 0 none (master port can be derived from another ds21q59 in the system.) 0 0 1 transceiver 1 0 1 0 transceiver 2 0 1 1 transceiver 3 1 0 0 transceiver 4 1 0 1 reserved for future use. 1 1 0 reserved for future use. 1 1 1 reserved for future use.
ds21q59 quad e1 transceiver 41 of 76 15. transmit clock source depending on the ds21q59?s operating mode, the transmit clock can be derived from different sources. in a basic configuration, where the ibo function is disabled, the transmit clock is normally sourced from the tclk pin. in this mode, a 2.048mhz clock with 50ppm accuracy is applied to the tclk pin. if the signal at tclk is lost, the ds21q59 automatically switches to either the system reference clock present on the refclk pin or to the recovered clock off the same port, depending on which source the host assigned as the backup clock. at the same time the host can be notified of the loss-of-transmit clock through an interrupt. the host can at any time force a switchover to one of the two backup clock sources regardless of the state of the tclk pin. when the ibo function is enabled, the transmit clock must be synchronous to the system clock since slips are not allowed in the transmit direction. in this mode, the tclk pin is ignored, and a transmit clock is automatically provided by the ibo circuit by dividing the clock present on the sysclk pin by 2, 4, or 8. in this configuration, if the signal present on the sysclk pin is lost, the ds21q59 automatically switches to either the system reference clock or to the recovered clock off the same port, depending on which source the host assigned as the backup clock. the host can at any time force a switchover to one of the two backup clock sources regardless of the state of the sysclk pin. 16. idle code insertion the transmit idle registers (tir1/2/3/4) determine which of the 32 e1 channels should be overwritten with the code placed in the transmit idle definition register (tidr). this allows the same 8-bit code to be placed into any of the 32 e1 channels. each of the bit positions in the transmit idle registers represents a ds0 channel in the outgoing frame. when these bits are set to 1, the corresponding channel transmits the idle code contained in the tidr. register name: tir1, tir2, tir3, tir4 register description: transmit idle registers register address: 24 hex, 25 hex, 26 hex, 27 hex bit # 7 6 5 4 3 2 1 0 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 name bit function ch1 to ch32 tir1.0 to 4.7 transmit idle code-insertion control bits 0 = do not insert the idle code in the tidr into this channel 1 = insert the idle code in the tidr into this channel register name: tidr register description: transmit idle definition register register address: 23 hex bit # 7 6 5 4 3 2 1 0 name tidr7 tidr6 tidr5 tidr4 tidr3 tidr2 tidr1 tidr0 name bit function tidr7 7 msb of the idle code (this bit is transmitted first.) tidr6 6 ? tidr5 5 ? tidr4 4 ? tidr3 3 ? tidr2 2 ? tidr1 1 ? tidr0 0 lsb of the idle cod e (this bit is transmitted last.)
ds21q59 quad e1 transceiver 42 of 76 17. per-channel loopback the ds21q59 has per-channel loopback capability that can operate in one of two modes: remote per-channel loopback or local per-channel loopback. pclb1/2/3/4 are used for both modes to determine which channels are looped back. in remote per-channel loopback mode, pclb1/2/3/4 determine which channels (if any) in the transmit direction should be replaced with the data from the receiver or, in other words, off the e1 line. in local per-channel loopback mode, pclb1/2/3/4 determine which channels (if any) in the receive direction should be replaced with the data from the transmit. if either mode is enabled, transmit and receive clocks and frame syncs must be synchronized. there are no restrictions on which channels can be looped back or on how many channels can be looped back. register name: pclb1, pclb2, pclb3, pclb4 register description: per-channel loopback registers register address: 2b hex, 2c hex, 2d hex, 2e hex bit # 7 6 5 4 3 2 1 0 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 name bit function ch1 to ch32 pclb1.0 to 4.7 per-channel loopback control bits 0 = do not loopback this channel 1 = loopback this channel 18. elastic store operation the ds21q59 contains a two-frame (512 bits) elastic store fo r the receive direction. the elastic store is used to absorb the differences in frequency and phase between the e1 data stream and an asynchronous (i.e., not frequency locked) backplane clock that can be 2.048mhz for normal operation or 4.096mhz, 8.192mhz, or 16.384mhz when using the ibo function. the elastic store contains full controlled slip capability. if the receive elastic store is enabled (rcr.4 = 1), the user must provide a 2.048mhz clock to the sysclk pin. if the ibo function is enabled, a 4.096mhz, 8.192mhz, or 16.384mhz clock must be provided at the sysclk pin. the user has the option of either providing a frame/mult iframe sync at the rsync pin (rcr.5 = 1) or having the rsync pin provide a pulse on frame/multiframe boundaries (rcr. 5 = 0). if the user wishes to obtain pulses at the frame boundary, rcr1.6 must be set to 0; if the user wishes to have pulses occur at the multiframe boundary, rcr1.6 must be set to 1. if the elastic store is enabled, either cas (rcr.7 = 0) or crc4 (rcr.7 = 1) multiframe boundaries are indicated through the rsync output. see section 24 for timing details. if the 512-bit elastic buffer either fills or empties, a controlled slip occurs. if the buffer empties, a full frame of data (256 bits) is repeated at rser, and the sr1.4 and rir.3 bits are set to 1. if the buffer fills, a full frame of data is deleted, and the sr1.4 and rir.4 bits are set to 1.
ds21q59 quad e1 transceiver 43 of 76 19. additional (sa) and international (si) bit operation on the receiver, the raf and rnaf registers always report the data as it is received in the additional (sa) and international (si) bit locations. the raf and rnaf registers are updated with the setting of the receive align frame bit in status register 2 (sr2.6). the host can use the sr2.6 bit to know when to read the raf and rnaf registers. it has 250 s to retrieve the data before it is lost. on the transmitter, data is sampled from the taf and tnaf registers with the setting of the transmit align frame bit in status register 2 (sr2.3). the host can use the sr2.3 bit to know when to update the taf and tnaf registers. it has 250 s to update the data or else the old data is retransmitted. data in the si bit position is overwritten if either the framer is programmed (1) to source the si bits from the tser pin, (2) in the crc4 mode, or if the framer (3) has automatic e-bit insertion enabled. data in the sa bit position is overwritten if any of the tcr.3?tcr.7 bits are set to 1. please see the tcr register descriptions for more details. register name: raf register description: receive align frame register register address: 28 hex bit # 7 6 5 4 3 2 1 0 name si 0 0 1 1 0 1 1 name bit function si 7 international bit 0 6 frame alignment signal bit 0 5 frame alignment signal bit 1 4 frame alignment signal bit 1 3 frame alignment signal bit 0 2 frame alignment signal bit 1 1 frame alignment signal bit 1 0 frame alignment signal bit register name: rnaf register description: receive nonalign frame register register address: 29 hex bit # 7 6 5 4 3 2 1 0 name si 1 a sa4 sa5 sa6 sa7 sa8 name bit function si 7 international bit 1 6 frame nonalignment signal bit a 5 remote alarm sa4 4 additional bit 4 sa5 3 additional bit 5 sa6 2 additional bit 6 sa7 1 additional bit 7 sa8 0 additional bit 8
ds21q59 quad e1 transceiver 44 of 76 register name: taf register description: transmit align frame register register address: 20 hex bit # 7 6 5 4 3 2 1 0 name si 0 0 1 1 0 1 1 note: this register must be programmed with the 7-bit fas word. the ds21q59 does not automatically set these bits. name bit function si 7 international bit 0 6 frame alignment signal bit. set this bit = 0. 0 5 frame alignment signal bit. set this bit = 0. 1 4 frame alignment signal bit. set this bit = 1. 1 3 frame alignment signal bit. set this bit = 1. 0 2 frame alignment signal bit. set this bit = 0. 1 1 frame alignment signal bit. set this bit = 1. 1 0 frame alignment signal bit. set this bit = 1. register name: tnaf register description: transmit nonalign frame register register address: 21 hex bit # 7 6 5 4 3 2 1 0 name si 1 a sa4 sa5 sa6 sa7 sa8 note: bit 6 must be programmed to 1. the ds21q59 does not automatically set this bit. name bit function si 7 international bit 1 6 frame nonalignment signal bit. set this bit = 1. a 5 remote alarm (used to transmit the alarm.) sa4 4 additional bit 4 sa5 3 additional bit 5 sa6 2 additional bit 6 sa7 1 additional bit 7 sa8 0 additional bit 8
ds21q59 quad e1 transceiver 45 of 76 20. user-configurable outputs there are two user-configurable output pins for each transceiver, outa and outb. these pins can be programmed to output various clocks, alarms for line monitoring, or logic 0 and 1 levels to control external circuitry. they can also be used to access transmit data between the framer and transmit liu. outa and outb can be active low or active high when operating as clock and alarm outputs. outa is active high if outac.4 = 1 and active low if outac.3 = 0. outb is active high if outbc.4 = 1 and active low if outbc.4 = 0 ( table 20-a ). select mode 0000 to control external circuitry. in this configuration, the outa pin follows outac.4 and the outb pin follows outbc.4. the outac register also contains a control bit for cmi operation. see section 22 for details about cmi operation. register name: outac register description: outa control register register address: 1a hex bit # 7 6 5 4 3 2 1 0 name ttlie cmii cmie oa4 oa3 oa2 oa1 oa0 name bit function ttlie 7 ttl input enable. when this bit is set, the receiver can accept ttl positive and negative data at the rtip and rring inputs. the data is clocked in on the falling edge of mclk. cmii 6 cmi invert. see section 22 for details. 0 = cmi input data not inverted 1 = cmi input data inverted cmie 5 cmi enable. see section 22 for details. 0 = cmi disabled 1 = cmi enabled oa4 4 outa control bit 4. inverts outa output. oa3 3 outa control bit 3. see table 20-a for details. oa2 2 outa control bit 2. see table 20-a for details. oa1 1 outa control bit 1. see table 20-a for details. oa0 0 outa control bit 0. see table 20-a for details. register name: outbc register description: outb control register register address: 1b hex bit # 7 6 5 4 3 2 1 0 name nrze ? ? ob4 ob3 ob2 ob1 ob0 name bit function nrze 7 nrz enable. when this bit is set, the receiver can accept ttl-type nrz data at the rtip input. rring becomes a clock input. 0 = rtip and rring are in normal mode. 1 = rtip becomes an nrz ttl-type input and rring is its associated clock input. data at rtip is clocked in on the falling edge of the clock present on rring. ? 6 unused. should be set = 0 for proper operation. ? 5 unused. should be set = 0 for proper operation. ob4 4 outb control bit 4. inverts outb output. ob3 3 outb control bit 3 ob2 2 outb control bit 2 ob1 1 outb control bit 1 ob0 0 outb control bit 0
ds21q59 quad e1 transceiver 46 of 76 table 20-a. outa and outb function select oa3 ob3 oa2 ob2 oa1 ob1 oa0 ob0 function 0 0 0 0 external hardware control bit . in this mode, outa and outb can be used as simple control pins for external circuitry. use oa4 and ob4 to toggle outa and outb. 0 0 0 1 rclk . receive recovered clock. 0 0 1 0 receive loss-of-sync indicator . real-time hardware version of sr1.0 ( table 9-a ). 0 0 1 1 receive loss-of-carrier indicator . real-time hardware version of sr1.1 ( table 9-a ). 0 1 0 0 receive remote alarm indicator . real-time hardware version of sr1.2 ( table 9-a ). 0 1 0 1 receive unframed all-ones indicator. real-time hardware version of sr1.3 ( table 9-a ). 0 1 1 0 receive slip-occurrence indicator . one-clock-wide pulse for every slip of the receive elastic store. hardware version of sr1.4. 0 1 1 1 receive crc error indicator . one-clock-wide pulse for every multiframe that contains a crc error. output forced to 0 during loss of sync. 1 0 0 0 loss-of-transmit clock indicator . real-time hardware version sr2.2 ( table 9-a ). 1 0 0 1 rfsync . recovered frame-sync pulse. 1 0 1 0 prbs bit error . a half-clock-wide pulse for every bit error in the received prbs pattern. 1 0 1 1 tdata/rdata . outb outputs an nrz version of the transmit data stream (tdata) prior to the transmit line interface. outa outputs the received serial data stream (rdata) prior to the elastic store. 1 1 0 0 receive crc4 multiframe sync . recovered crc4 mf sync pulse. 1 1 0 1 receive cas multiframe sync . recovered cas mf sync pulse. 1 1 1 0 transmit current limit . real-time indicator that the ttip and tring outputs have reached their 50ma current limit. 1 1 1 1 tpos/tneg output . this mode outputs the ami/hdb3 encoded transmit data. outa outputs tneg data. outb outputs tpos data.
ds21q59 quad e1 transceiver 47 of 76 21. line interface unit the line interface unit contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the e1 line; and the jitter attenuator. the line interface control register (licr), described below, controls each of these three sections. register name: licr register description: line interface control register register address: 17 hex bit # 7 6 5 4 3 2 1 0 name l2 l1 l0 egl jas jabds dja tpd name bit function l2 7 line build-out select bit 2. sets the transmitter build-out. l1 6 line build-out select bit 1. sets the transmitter build-out. l0 5 line build-out select bit 0. sets the transmitter build-out. egl 4 receive equalizer gain limit 0 = -12db 1 = -43db jas 3 jitter attenuator select 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side jabds 2 jitter attenuator buffer depth select 0 = 128 bits 1 = 32 bits (use for delay-sensitive applications) dja 1 disable jitter attenuator 0 = jitter attenuator enabled 1 = jitter attenuator disabled tpd 0 transmit power-down 0 = powers down the transmitter and tri-states the ttip and tring pins 1 = normal transmitter operation 21.1 receive clock and data recovery the ds21q59 contains a digital clock recovery system. (see figure 3-1 and figure 21-1 for more details.) the device couples to the receive e1 shielded twisted pair or coax through a 1:1 transformer ( table 21-b ). the 2.048mhz clock attached at the mclk pin is internally multiplied by 16 through an internal pll and fed to the clock recovery system. the clock recovery system uses the clock from the pll circuit to form a 16 times oversampler, which is used to recover the clock and data. this oversampling technique offers outstanding jitter tolerance ( figure 21-4 ). normally, rclk is the recovered clock from the e1 ami/hdb3 waveform presented at the rtip and rring inputs. when no ami signal is present at rtip and rring, an rcl condition occurs and the rclk is sourced from the clock applied at the mclk pin. if the jitter attenuator is either placed in the transmit path or is disabled, rclk can exhibit slightly shorter high cycles of the clock. this is because of the highly oversampled digital clock recovery circuitry. if the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the rclk to being close to 50% duty cycle. see receive ac characteristics in section 26.4 for more details. 21.1.1 termination the ds21q59 is designed to be fully software-selectable for 75 and 120 termination without the need to change any external resistors. the user can configure the ds21q59 for 75 or 120 receive termination by setting the irtsel (ccr5.4) bit. when using the internal termination feature, the external termination resistance should be 120 (typically two 60 resistors). setting irtsel = 1 causes the ds21q59 to internally apply parallel resistance to the external resistors to adjust the termination to 75 ( figure 21-2 ).
ds21q59 quad e1 transceiver 48 of 76 21.2 transmit waveshaping and line driving the ds21q59 uses a set of laser-trimmed delay lines and a precision digital-to-analog converter (dac) to create the waveforms that are transmitted onto the e1 line. the waveforms meet the itu g.703 specifications ( figure 21-3 ). the user selects which waveform is to be generated by properly programming the l2/l1/l0 bits in the line interface control register (licr). the ds21q59 can be set up in a number of various configurations depending on the application ( table 21-a ). table 21-a. line build-out select in licr l2 l1 l0 application transformer return loss * rt ( ) ** 0 0 0 75 normal 1:2 step-up n.m. 0 0 0 1 120 normal 1:2 step-up n.m. 0 0 1 0 75 with protection resistors 1:2 step-up n.m. 2.5 0 1 1 120 with protection resistors 1:2 step-up n.m. 2.5 1 0 0 75 with high return loss 1:2 step-up 21db 6.2 1 0 1 120 with high return loss 1:2 step-up 21db 11.6 * n.m. = not meaningful (return loss value too low for significance) ** see application note 336: transparent operation on t1, e1 framers and transceivers for details on e1 line interface design. because of the nature of the transmitter?s design, very little jitter (less than 0.005ui p-p broadband from 10hz to 100khz) is added to the jitter present on tclk (or source used for transmit clock). also, the waveform created is independent of the duty cycle of tclk. the transmitter in the device couples to the e1 transmit-shielded twisted pair or coax through a 1:2 step-up transformer, as shown in figure 21-1 . for the devices to create the proper waveforms, the transformer used must meet the specifications listed in table 21-b . the line driver in the device contains a current limiter that prevents more than 50ma (rms) from being sourced in a 1 load. table 21-b. transformer specifications specification recommended value turns ratio 1:1 (receive) and 1:2 (transmit) 3% primary inductance 600 h minimum leakage inductance 1.0 h maximum intertwining capacitance 40pf maximum dc resistance 1.2 maximum figure 21-1. external analog conn ections (basic configuration) rtip rring ttip tring e1 transmit line ds21q59 0.47 f ( nonpolarized ) dvdd dvss 0.1 f rvdd rvss 0.1 f tvdd tvss 0.1 f +3.3v rr 0.1 f 0.01 f 2.048mhz mclk 1 : 1 2 : 1 rr 1/4 e1 receive line
ds21q59 quad e1 transceiver 49 of 76 figure 21-2. external analog connections (protected interface) rtip1 rring1 ttip1 tring1 1/4 ds21q59 0.47 f (nonpolarized ) dvdd dvss 0.1 f rvdd rvss 0.1 f +vdd 0.01 f 2.048mhz mclk s 1:1 0.1 f fuse fuse 60 60 +vdd c2 d5 d6 d7 d8 68 f s transmi t line fuse fuse 0.1 f +vdd c1 d1 d2 d3 d4 tvdd tvss 2:1 receive line note 1: all resistor values are 1%. note 2: c1 = c2 = 0.1 f. note 3: s is a 6v transient suppressor. note 4: d1 to d8 are schottky diodes. note 5: the fuses are optional to prevent ac power line crosses from compromising the transformers. note 6: the 68 f is used to keep the local power plane potential within tolerance during a surge.
ds21q59 quad e1 transceiver 50 of 76 figure 21-3. transmit waveform template 21.3 jitter attenuators the ds21q59 contains an on-board clock and data jitter attenuator for each transceiver and a single, undedicated ?clock only? jitter attenuator. this undedicated jitter attenuator is shown in the block diagram ( figure 3-1 ) as the alternate jitter attenuator. 21.3.1 clock and data jitter attenuators the clock and data jitter attenuators can be mapped into the receive or transmit paths and can be set to buffer depths of either 32 or 128 bits through the licr. the 128-bit mode is used in applications where large excursions of wander are expected. the 32-bit mode is used in delay-sensitive applications. the characteristics of the attenuators are shown in figure 21-5 . the jitter attenuators can be placed in either the receive path or the transmit path by appropriately setting or clearing the jas bit in the licr. also, setting the dja bit in the licr can disable the jitter attenuator (in effect, remove it). for the jitter attenuator to operate properly, a 2.048mhz clock (50ppm) must be applied at the mclk pin. on-board circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the tclki pin to create a smooth jitter-free clock that is used to clock data out of the jitter attenuator fifo. it is acceptable to provide a gapped/bursty clock at the tclki pin if the jitter attenuator is placed on the transmit side. if the incoming jitter exceeds either 120ui p-p (buffer depth is 128 bits) or 28ui p-p (buffer depth is 32 bits), the ds21q59 divides the internal nominal 32.768mhz clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. when the device divides by either 15 or 17, it also sets the jitter attenuator limit trip (jalt) bit in the receive information register (rir.5). 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 time (ns) scaled amplitude 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (in 75 systems, 1.0 on the scale = 2.37vpeak in 120 systems, 1.0 on the scale = 3.00vpeak) g.703 template
ds21q59 quad e1 transceiver 51 of 76 21.3.2 undedicated clock jitter attenuator the undedicated jitter attenuator is useful for preparing a user-supplied clock for use as a transmission clock (tclk). ajacki is the input pin and ajcako is the output pin. clocks generated by certain types of pll or other synthesizers can contain too much jitter to be appropriate for transmission. network requirements limit the amount of jitter that can be transmitted onto the network. this feature is enabled by setting sc1cr.7 = 1 in transceiver 1. figure 21-4. jitter tolerance figure 21-5. jitter attenuation frequency (hz) unit intervals (ui p-p ) 1k 100 10 1 0.1 10 100 1k 10k 100k ds21q59 tolerance 1 minimum tolerance level as per itu g.823 40 1.5 0.2 20 2.4k 18k frequency (hz) 0 -20 -60 1 10 100 1k 10k jitter attenuation (db) 100k itu g.7xx prohibited area ets 300 011 and tbr12 prohibited area 40 -40 jitter attenuation curve
ds21q59 quad e1 transceiver 52 of 76 22. code mark inversion (cmi) the ds21q59 provides a cmi interface for connecting to optical transports. this interface is a unipolar 1t2b- coded signal. ones are alternately encoded as a logical 1 or 0 level for the full duration of the clock period. zeros are encoded as a 0-to-1 transition at the middle of the clock period. figure 22-1 shows an example data pattern and its cmi result. the control bit for enabling cmi is in the outac register, as shown below. register name: outac register description: outa control register register address: 1a hex bit # 7 6 5 4 3 2 1 0 name ttlie cmii cmie oa4 oa3 oa2 oa1 oa0 name bit function ttlie 7 ttl input enable. when this bit is set, the receiver can accept ttl positive and negative data at the rtip and rring inputs. the data is clocked in on the falling edge of mclk. cmii 6 cmi invert 0 = cmi input data not inverted 1 = cmi input data inverted cmie 5 transmit and receive cmi enable 0 = transmit and receive line interface operates in normal ami/hdb3 mode 1 = transmit and receive line interface operate in cmi mode. ttip is cmi output and rtip is cmi input. in this mode of operation tring and rring are no connects. oa4 4 outa control bit 4. inverts outa output. oa3 3 outa control bit 3. see table 20-a for details. oa2 2 outa control bit 2. see table 20-a for details. oa1 1 outa control bit 1. see table 20-a for details. oa0 0 outa control bit 0. see table 20-a for details. figure 22-1. cmi coding 0 1 1 1 0 0 1 clock data cmi
ds21q59 quad e1 transceiver 53 of 76 transmit and receive cmi is enabled through outac.7. when this register bit is set, the ttip pin outputs cmi- coded data at normal ttl-type levels. this signal can be used to directly drive an optical interface. when cmi is enabled, the user can also use hdb3 coding. when this register bit is set, the rtip pin becomes a unipolar cmi input. the cmi signal is processed to extract and align the clock with data. the bipolar code-violation counter counts cvs in the cmi signal. cvs are defined as consecutive 1s of the same polarity, as shown in figure 22-2 . if hdb3 precoding is enabled, the cvs generated by hdb3 are not counted as errors. figure 22-2. example of cmi code violation 0 1 1 1 0 0 1 clock dat a cmi code violation
ds21q59 quad e1 transceiver 54 of 76 23. interleaved pcm bus operation in many architectures, the pcm outputs of individual framers are combined into higher-speed pcm buses to simplify transport across the system backplane. the ds21q59 can be configured to allow pcm data buses to be multiplexed into higher-speed data buses, eliminating external hardware and saving board space and cost. the ds21q59 uses a channel interleave method. see figure 24-4 and figure 24-7 for details of the channel interleave. the interleaved pcm bus option supports three bus speeds. the 4.096mhz bus speed allows two pcm data streams to share a common bus. the 8.192mhz bus speed allows four pcm data streams to share a common bus. the 16.384mhz bus speed allows eight pcm data streams to share a common bus. see figure 23-1 for an example of four transceivers sharing a common 8.192mhz pcm bus. the receive elastic stores of each transceiver must be enabled. through the ibo register the user can configure each transceiver for a specific bus speed and position. for all ibo bus configurations each transceiver is assigned an exclusive position in the high-speed pcm bus. when the device is configured for ibo operation, the tsyncx pin should be configured as an output or as an input connected to ground. the user cannot supply a tsyncx signal in this mode. when ibo operation is enabled, tsyncx will be internally tied to rsyncx. if tsyncx is configured as an input, the physical pin will be disconnected from the internal tsyncx signal and should therefore be connected to ground to keep it from floating. register name: ibo register description: interleave bus operation register register address: 1c hex bit # 7 6 5 4 3 2 1 0 name ? ibotcs scs1 sc s0 iboen da2 da1 da0 name bit function ? 7 not assigned. should be set to 0. ibotcs 6 ibo transmit clock source 0 = tclk pin is the source of transmit clock 1 = transmit clock is internally derived from the clock at the sysclk pin scs1 5 system clock select bit 1 ( table 23-a ) scs0 4 system clock select bit 0 ( table 23-a ) iboen 3 interleave bus operation enable 0 = ibo disabled 1 = ibo enabled da2 2 device assignment bit 3 ( table 23-b ) da1 1 device assignment bit 2 ( table 23-b ) da0 0 device assignment bit 1 ( table 23-b ) table 23-a. ibo system clock select scs1 scs0 function 0 0 2.048mhz, single device on bus 0 1 4.096mhz, two devices on bus 1 0 8.192mhz, four devices on bus 1 1 16.384mhz, eight devices on bus table 23-b. ibo device assignment da2 da1 da0 function 0 0 0 1st device on bus 0 0 1 2nd device on bus 0 1 0 3rd device on bus 0 1 1 4th device on bus 1 0 0 5th device on bus 1 0 1 6th device on bus 1 1 0 7th device on bus 1 1 1 8th device on bus
ds21q59 quad e1 transceiver 55 of 76 figure 23-1. ibo configuration using two ds21q59 transceivers (eight e1 lines) xfmr xfmr xfmr xfmr xfmr xfmr xfmr xfmr xfmr xfmr xfmr xfmr xfmr xfmr xfmr xfmr ds21q59 ds21q59 pcm in pcm out 16.384mhz interleaved pcm bus 16.384mhz clock derived from one of the eight e1 lines e1 #1 e1 #2 e1 #3 e1 #4 e1 #5 e1 #6 e1 #7 e1 #8 rser1 rser2 rser3 rser4 tser1 tser2 tser3 tser4 rser1 rser2 rser3 rser4 tser1 tser2 tser3 tser4 4/8/16mck 4/8/16mck refclk refclk rtip1/rring1 ttip1/tring1 rtip2/rring2 ttip2/tring2 rtip3/rring3 ttip3/tring3 rtip4/rring4 ttip4/tring4 rtip1/rring1 ttip1/tring1 rtip2/rring2 ttip2/tring2 rtip3/rring3 ttip3/tring3 rtip4/rring4 ttip4/tring4 sysclk1 sysclk2 sysclk3 sysclk4 sysclk1 sysclk2 sysclk3 sysclk4 tsync1 rsync2 rsync3 rsync4 rsync4 rsync3 rsync2 rsync1 rsync1 note: see section 21 for details on line interface circuit.
ds21q59 quad e1 transceiver 56 of 76 24. functional timing diagrams 24.1 receive figure 24-1. receive frame and multiframe timing figure 24-2. receive boundary timing (with elastic store disabled) figure 24-3. receive boundary timi ng (with elastic store enabled) frame# 1 23456789101112131415161 rsync 1 rsync 2 note 1: rsync in frame/output mode (rcr.6 = 0). note 2: rsync in multiframe/output mode (rcr.6 = 1). this diagram assumes the cas mf begins in the raf frame. channel 32 channel 1 channel 2 rclk rser rsync lsb msb si 1 a sa4 sa5 sa6 sa7 sa8 rser channel 1 sysclk rsync channel 31 channel 32 1 rsync 2 lsb msb lsb msb note 1: rsync is in the output mode (rcr.5 = 0). note 2: rsync is in the input mode (rcr.5 = 1). rsync may be held high for multiple clock cycles as long a s it transitions low one clock cycle before transitioning high again for the next sync pulse.
ds21q59 quad e1 transceiver 57 of 76 figure 24-4. receive interleave bus operation rser lsb sysclk rsync framer 3, channel 32 msb lsb framer 0, channel 1 msb lsb framer 1, channel 1 4 rser rsync rser fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 1 2 bit detail fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 note 1: 4.096mhz bus configuration. note 2: 8.192mhz bus configuration. note 3: 16.384mhz bus configuration. note 4: rsync is in the input mode (rcr.5 = 1). rsync may be held high for multiple clock cycles as long as it transitions low one clock cycle before transitioning high again for the next sync pulse. rser fr4 ch32 fr5 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 3 fr6 ch32 fr7 ch32 fr4 ch1 fr5 ch1 fr6 ch1 fr7 ch1 fr4 ch2 fr5 ch2 fr6 ch2 fr7 ch2
ds21q59 quad e1 transceiver 58 of 76 24.2 transmit figure 24-5. transmit frame and multiframe timing figure 24-6. transmit boundary timing 12345 678910 11 12 1 frame# tsync tsync 13 14 15 16 12345 14 15 16 678910 2 note 1: tsync in frame mode (tcr.1 = 0). note 2: tsync in multiframe mode (tcr.1 = 1). lsb msb lsb msb channel 1 channel 2 tclk tser tsync tsync 1 2 si 1 a sa4 sa5 sa6 sa7 sa8 note 1: tsync is in the output mode (tcr.0 = 1). note 2: tsync is in the input mode (tcr.0 = 0). tsync may be held high for multiple clock cycles as long a s it transitions low one clock cycle before transitioning high again for the next sync pulse.
ds21q59 quad e1 transceiver 59 of 76 figure 24-7. transmit interleave bus operation tser lsb sysclk tsync framer 3, channel 32 msb lsb framer 0, channel 1 msb lsb framer 1, channel 1 4 tser tsync tser fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 1 2 bit detail fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 note 1: 4.096mhz bus configuration. note 2: 8.192mhz bus configuration. note 3: 16.384mhz bus configuration. note 4: tsync is in the input mode (tcr.0 = 0). tsync may be held high for multiple clock cycles as long as it transitions low one clock cycle before transitioning high again for the next sync pulse. tser fr4 ch32 fr5 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 3 fr6 ch32 fr7 ch32 fr4 ch1 fr5 ch1 fr6 ch1 fr7 ch1 fr5 ch2 fr6 ch2
ds21q59 quad e1 transceiver 60 of 76 figure 24-8. framer synchronization flowchart fas resync criteria met check for >=915 out of 1000 crc4 word errors 8ms ti me out rlos = 1 set fasrc (rir.1) cas resync criteria met; set casrc (rir.0) fas search fassa = 1 fas sync criteria met fassa = 0 cas sync criteria met cassa = 0 if crc4 is on (ccr1.0 = 1) rlos = 1 if cas is on (ccr1.3 = 0) power up increment crc4 sync counter; crc4sa = 0 crc4 resync crit eri a met (rir.2) cas mul ti frame search (if enabled vi a ccr1.3) cassa = 1 crc4 mult iframe search (if enabled vi a ccr1.0) crc4sa = 1 resync i f rcr1. 0 = 0 check for fas framing error (depends on rcr1.2) check for cas mf word error sync decl ared rlos = 0 crc4 sync cri t eri a met ; crc4sa = 0; reset crc4 sync counter
ds21q59 quad e1 transceiver 61 of 76 figure 24-9. transmit data flow si bit insertion control (tcr.3) timeslot 0 pass-through (tcr.6) e-bit generation (tcr.5) idle code / channel insertion control via tir1/2/3/4 transmit unframed all ones (tcr.4) or auto ais (ccr2.5) code word generation crc4 enable (ccr.4) taf tnaf.5-7 tidr to waveshaping and line drivers 01 0 1 01 1 0 0 = register = device pin = selector key: notes: 1. auto remote alarm if enabled will only overwrite bit 3 of timeslot 0 in the not align frames if the alarm needs to be sent. crc4 multiframe alignment word generation (ccr.4) receive side crc4 error detector auto remote alarm generation (ccr.4) tser ami or hdb3 converter ccr.6 1 1 sa1 - sa16 signaling insertion ccr6.3 01
ds21q59 quad e1 transceiver 62 of 76 25. operating parameters absolute maximum ratings voltage range on any pin relative to ground -1.0v to +6.0v operating temperature range for ds21q59l 0c to +70c operating temperature range for DS21Q59LN -40c to +85c storage temperature range -55c to +125c soldering temperature range see ipc/jedec j-std-020a specification stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device. recommended dc operating conditions (t a = 0c to +70c for ds21q59l; t a = -40c to +85c for DS21Q59LN.) parameter symbol conditions min typ max units logic 1 v ih 2.0 5.5 v logic 0 v il -0.3 +0.8 v supply v dd (note 1) 3.135 3.3 3.465 v capacitance (t a = +25c) parameter symbol conditions min typ max units input capacitance c in 5 pf output capacitance c out 7 pf dc characteristics (v dd = 3.3v 5%, t a = 0c to +70c for ds21q59l; v dd = 3.3v 5%, t a = -40c to +85c for DS21Q59LN.) parameter symbol conditions min typ max units supply current at 3.3v i dd (note 2) 230 ma input leakage i il (note 3) -1.0 +1.0 a output leakage i lo (note 4) +1.0 a output current (2.4v) i oh -1.0 ma output current (0.4v) i ol +4.0 ma note 1: applies to rvdd, tvdd, and dvdd. note 2: tclks = sysclks = mclk = 2.048mhz; outputs open circuited; ttips and trings driving 30 ; qrss data pattern. 0.0v < v in < v dd . note 3: applied to int when tri-stated. note 4: applies to output pins in a tri-state condition.
ds21q59 quad e1 transceiver 63 of 76 26. ac timing parameters and diagrams 26.1 multiplexed bus ac characteristics table 26-a. ac characteristics?multiplexed parallel port (v dd = 3.3v 5%, t a = 0c to +70c for ds21q59l; v dd = 3.3v 5%, t a = -40c to +85c for DS21Q59LN.) ( figure 26-1 , figure 26-2 , and figure 26-3 ) parameter symbol conditions min typ max units cycle time t cyc 200 ns pulse width, ds low or rd high pw el 100 ns pulse width, ds high or rd low pw eh 100 ns input rise/fall times t r , t f 20 ns r/ w hold time t rwh 10 ns r/ w setup time before ds high t rws 50 ns cs setup time before ds, wr , or rd active t cs 20 ns cs hold time t ch 0 ns read data hold time t dhr 10 50 ns write data hold time t dhw 0 ns muxed address valid to as or ale fall t asl 15 ns muxed address hold time t ahl 10 ns delay time ds, wr, or rd to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr, or rd t ased 10 ns output data-delay time from ds or rd t ddr 20 140 ns data setup time t dsw 50 ns
ds21q59 quad e1 transceiver 64 of 76 figure 26-1. intel bus read ac timing (pbts = 0) figure 26-2. intel bus write timing (pbts = 0) ash pw t cyc t asd t asd pw pw eh el t t t t t t ahl ch cs asl ased c s ad0?ad7 dhr t ddr ale r d w r ash pw t cyc t asd t asd pw pw eh el t t t t t t t ahl dsw dhw ch cs asl ased c s ad0?ad7 r d w r ale
ds21q59 quad e1 transceiver 65 of 76 figure 26-3. motorola bus ac timing (pbts = 1) t asd ash pw t t asl ahl t cs t asl t t t dsw dhw t ch t t t ddr dhr rwh t ased pw eh t rws ahl pw el t cyc as ds ad0?ad7 (write) ad0?ad7 (read) r / w c s
ds21q59 quad e1 transceiver 66 of 76 26.2 nonmultiplexed bus ac characteristics table 26-b. ac characteristics?nonmultiplexed parallel port (v dd = 3.3v 5%, t a = 0c to +70c for ds21q59l; v dd = 3.3v 5%, t a = -40c to +85c for DS21Q59LN.) ( figure 26-4 through figure 26-7 ) parameter symbol conditions min typ max units setup time for a0 to a7, valid to cs active t1 0 ns setup time for cs active to either rd , wr , or ds active t2 0 ns delay time from either rd or ds active to data valid t3 140 ns hold time from either rd , wr , or ds inactive to cs inactive t4 0 ns hold time from cs inactive to data bus tri-state t5 5.0 20 ns wait time from either wr or ds active to latch data t6 75 ns data setup time to either wr or ds inactive t7 10 ns data hold time from either wr or ds inactive t8 10 ns address hold from either wr or ds inactive t9 10 ns figure 26-4. intel bus read timing (pbts = 0) address valid data valid a0?a7 d0?d7 w r c s r d 0ns min 0ns min 75ns max 0ns min 5ns min/20ns max t1 t2 t3 t4 t5
ds21q59 quad e1 transceiver 67 of 76 figure 26-5. intel bus write timing (pbts = 0) figure 26-6. motorola bus read timing (pbts = 1) figure 26-7. motorola bus write timing (pbts = 1) address valid a0?a7 d0?d7 r d c s w r 0ns min 0ns min 75ns min 0ns min 10ns min 10ns min t1 t2 t6 t4 t7 t8 address valid data valid a0?a7 d0?d7 r/ w c s d s 0ns min 0ns min 75ns max 0ns min 5ns min/20ns max t1 t2 t3 t4 t5 address valid a0?a7 d0?d7 r/ w c s d s 0ns min 0ns min 75ns min 0ns min 10ns min 10ns min t1 t2 t6 t4 t7 t8
ds21q59 quad e1 transceiver 68 of 76 26.3 serial port table 26-c. ac characteristics?serial port (bts1 = 1, bts0 = 0) (v dd = 3.3v 5%, t a = 0c to +70c for ds21q59l; v dd = 3.3v 5%, t a = -40c to +85c for DS21Q59LN.) ( figure 26-8 ) parameter symbol conditions min typ max units setup time cs to sclk t css 50 ns setup time sdi to sclk t sss 50 ns hold time sclk to sdi t ssh 50 ns sclk high/low time t slh 200 ns sclk rise/fall time t srf 50 ns sclk to cs inactive t lsc 50 ns cs inactive time t cm 250 ns sclk to sdo valid t ssv 50 ns sclk to sdo tri-state t ssh 100 ns cs inactive to sdo tri-state t csh 100 ns figure 26-8. serial bus timing (bts1 = 1, bts0 = 0) sclk 1 sclk 2 sdi cs high-z sdo t css t sss t ssh t srf t slh t lsc t cm t ssv t ssh t csh high-z lsb lsb lsb msb msb msb note 1: oces = 1 and ices = 0. note 2: oces = 0 and ices = 1.
ds21q59 quad e1 transceiver 69 of 76 26.4 receive ac characteristics table 26-d. ac characteristics?receiver (v dd = 3.3v 5%, t a = 0c to +70c for ds21q59l; v dd = 3.3v 5%, t a = -40c to +85c for DS21Q59LN.) ( figure 26-9 and figure 26-10 ) parameter symbol conditions min typ max units (note 1) 648 (note 2) 488 (note 3) 244 (note 4) 122 sysclk period t sp (note 5) 61 ns t sh 20 0.5 t sp sysclk pulse width t sl 20 0.5 t sp ns rsync setup to sysclk falling t su 20 ns rsync hold from sysclk falling t hd 20 ns rsync pulse width t pw 50 ns delay rclk to rser valid t d1 50 ns delay rclk to rsync, outa, outb t d2 50 ns delay sysclk to rser valid t d3 22 ns delay sysclk to rsync, outa, outb t d4 22 ns note 1: sysclk = 1.544mhz. note 2: sysclk = 2.048mhz. note 3: sysclk = 4.096mhz. note 4: sysclk = 8.192mhz. note 5: sysclk = 16.384mhz.
ds21q59 quad e1 transceiver 70 of 76 figure 26-9. receive ac timing (receive elastic store disabled) t d1 t d2 rse r rsync 3 outa/outb 2 ( r clk ) msb of channel 1 outa/outb 4 outa/outb 5 outa/outb 1 (rclk) note 1: outa or outb configured to output rclk (noninverted). note 2: outa or outb configured to output rclk (inverted). note 3: rsync is in the output mode (rcr1.5 = 0). note 4: outa or outb configured to output rfsync , crc4 mf sync, or cas mf sync (noninverted). note 5: outa or outb configured to output rfsync, crc4 mf sync, or cas mf sync (inverted).
ds21q59 quad e1 transceiver 71 of 76 figure 26-10. receive ac timing (receive elastic store enabled) t f t r t d3 t d4 t t su hd rse r rsync 1 rsync 3 sysclk sl t t sp sh t msb of channel 1 outa/outb 2 note 1: rsync is in the output mode (rcr.5 = 0). note 2: outa or outb configured as crcr mf sync or cas mf sync. note 3: rsync is in the input mode (rcr.5 = 1).
ds21q59 quad e1 transceiver 72 of 76 26.5 transmit ac characteristics table 26-e. ac characteristics?transmit (v dd = 3.3v 5%, t a = 0c to +70c for ds21q59l; v dd = 3.3v 5%, t a = -40c to +85c for DS21Q59LN.) ( figure 26-11 and figure 26-12 ) parameter symbol conditions min typ max units (note 1) 648 tclk period t cp (note 2) 488 ns t ch 20 0.5 t cp tclk pulse width t cl 20 0.5 t cp ns (note 1) 648 (note 2) 488 (note 3) 244 (note 4) 122 sysclk period t sp (note 5) 61 ns t sh 20 0.5 t sp sysclk pulse width t sl 20 0.5 t sp ns tsync setup to tclk t su 20 ns tsync pulse width t pw 50 ns tser setup to tclk or sysclk falling t su 20 ns tser hold from tclk or sysclk falling t hd 20 ns tclk rise and fall times t r , t f 25 ns note 1: sysclk = 1.544mhz. note 2: sysclk = 2.048mhz. note 3: sysclk = 4.096mhz. note 4: sysclk = 8.192mhz. note 5: sysclk = 16.384mhz.
ds21q59 quad e1 transceiver 73 of 76 figure 26-11. transmit ac timing (ibo disabled) t f t r tclk tser t t cl t ch cp tsync 1 tsync 2 t d2 t t su hd su outa/outb 3 t d2 note 1: tsync is in output mode (tcr.0 = 1). note 2: tsync is in input mode (tcr.0 = 0). tsync may be held high for multiple clock cycles as long as it transitions low at least two clock cycles before transitioning high again. note 3: applies to outa and outb when configured for tpos and tneg outputs.
ds21q59 quad e1 transceiver 74 of 76 figure 26-12. transmit ac timing (ibo enabled) 26.6 special modes ac characteristics table 26-f. ac characteristics?special modes (v dd = 3.3v 5%, t a = 0c to +70c for ds21q59l; v dd = 3.3v 5%, t a = -40c to +85c for DS21Q59LN.) ( figure 26-13 ) parameter symbol conditions min typ max units rtip period t cp 488 ns t ch 75 rtip pulse width t cl 75 ns rtip setup to rring falling t su 20 ns tser hold from tclk falling t hd 20 ns rtip, rring rise and fall times t r , t f 25 ns special mode: outbc.7 = 1. note: rtip and rring become nrz data and clock inputs. figure 26-13. nrz input ac timing rtip rring su cl t t cp ch t t hd t f t r t f t r sysclk tser t t sl t sh sp t su note: tser is only sampled on the falling edge of sysclk when the ibo mode is enabled. t hd
ds21q59 quad e1 transceiver 75 of 76 27. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo .)
ds21q59 quad e1 transceiver maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2004 maxim integrated products printed usa 76 of 76 28. revision history date description 042403 new product release. 090104 1) add 16mhz ibo timing diagram and ac characteristics 2) correct typos in figure 26-10. reference to rsync as an input, not an output as shown in note 3. 3) added clarification to section 23 regarding the tsyncx pin when the part is configured for ibo mode. 4) modified table 26-d for clarification and corrected values. 5) modified table 26-e for clarification and corrected values. 6) added thd parameter to figure 26-12. 7) added notes to figures 24-3, 24-4, 24-6, 24-7, 26-11 regarding the duration of the sync pin when configured as an input. 8) corrected typo on figure 24-4 note 3, incorrect bit value for rsync configured as an input. (should be rcr.5 = 1).

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